Forum: FPGA, VHDL & Co. Xilinx: CLK not placed in an optimal clock IOB site ?


von Gast (Gast)


Lesenswert?

Clock IO 'CCKL_X' not placed in an optimal clock IOB site. Please move 
this to a P-type IOB site.

Was heisst das ?

von Bernd G. (Gast)


Lesenswert?

Xilinx sagt dazu folgendes:

NOTE: The most common design mistake leading to this error results from 
a single-ended clock input being LOC'd to the N side of a differential 
pair of clock-capable I/O. Only the P side of the differential pair has 
the dedicated routing resource. When choosing a Global Clock IOB site, 
it is not enough to choose a site with "GC" in the pin definition. It is 
also necessary to choose the "P" side of a differential pair. For 
example, a pin definition of IO_L1P_GC_CC_LC_3 is valid as a Global 
Clock IOB site, whereas IO_L1N_GC_CC_LC_3 is not.

War es das?

Also, Takt ans Plusbein legen!

Bitte melde dich an um einen Beitrag zu schreiben. Anmeldung ist kostenlos und dauert nur eine Minute.
Bestehender Account
Schon ein Account bei Google/GoogleMail? Keine Anmeldung erforderlich!
Mit Google-Account einloggen
Noch kein Account? Hier anmelden.