1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.numeric_std.all;
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4 |
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5 | -- Generiert aus dem 50 MHz Takt einen 25 MHz Takt
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6 | -- Der VGA-Takt für eine Auflösung von 640x480 Bildpunkten
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7 | -- bei 60 Hz Bildwiederholfrequenz ist eigentlich 25,175 Hz
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8 | entity clock25_entity is
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9 | port
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10 | (
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11 | clock50 : in std_logic;
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12 | clock25 : out std_logic
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13 | );
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14 | end clock25_entity;
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15 |
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16 | architecture rtl of clock25_entity is
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17 | signal counter : integer range 0 to 1;
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18 | begin
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19 | -- Generiere einen 25 MHz Takt
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20 | process (clock50)
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21 | begin
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22 | if rising_edge(clock50)
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23 | then
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24 | if counter = 0
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25 | then
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26 | clock25 <= '1';
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27 | counter <= counter + 1;
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28 | else
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29 | clock25 <= '0';
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30 | counter <= counter - 1;
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31 | end if;
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32 | end if;
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33 | end process;
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34 |
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35 | end architecture rtl;
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36 |
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37 | -------------------------------------------------------------------------------------------------------
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38 |
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39 | library ieee;
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40 | use ieee.std_logic_1164.all;
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41 | use ieee.numeric_std.all;
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42 | use work.vga_control_package.all;
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43 |
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44 | -- Erzeuge die VSync und HSync Signale
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45 | -- und die aktuelle Position auf dem VGA-Bildschirm
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46 | entity universal_vga_controller is
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47 | port(
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48 | clock : in std_logic;
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49 | vga_mode : in vgamode_record;
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50 | vga_out : out vga_out_record
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51 | );
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52 | end universal_vga_controller;
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53 |
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54 | architecture rtl of universal_vga_controller is
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55 |
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56 | signal horizontal_counter : horizontal_position := (others => '0');
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57 | signal vertical_counter : vertical_position := (others => '0');
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58 | constant horizontal_start_of_output : integer range 0 to 144 := vga_mode.horizontal_sync_pulse_width + vga_mode.horizontal_back_porch;
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59 | constant horizontal_end_of_output : integer range 0 to 784 := horizontal_start_of_output + vga_mode.horizontal_display_time;
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60 | constant vertical_start_of_output : integer range 0 to 31 := vga_mode.vertical_sync_pulse_width + vga_mode.vertical_back_porch;
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61 | constant vertical_end_of_output : integer range 0 to 511 := vertical_start_of_output + vga_mode.vertical_display_time;
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62 | begin
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63 |
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64 | process (clock)
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65 | begin
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66 | if rising_edge(clock)
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67 | then
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68 | if (horizontal_counter >= horizontal_start_of_output) and (horizontal_counter < horizontal_end_of_output)
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69 | and (vertical_counter >= vertical_start_of_output) and (vertical_counter < vertical_end_of_output)
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70 | then
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71 | vga_out.blank <= '0';
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72 | else
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73 | vga_out.blank <= '1';
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74 | end if;
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75 |
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76 | if (horizontal_counter >= 1) and (horizontal_counter <= vga_mode.horizontal_sync_pulse_width)
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77 | then
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78 | if vga_mode.horizontal_sync_pulse_polarity = neg
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79 | then
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80 | vga_out.hsync <= '0';
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81 | else
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82 | vga_out.hsync <= '1';
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83 | end if;
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84 | else
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85 | if vga_mode.horizontal_sync_pulse_polarity = neg
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86 | then
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87 | vga_out.hsync <= '1';
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88 | else
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89 | vga_out.hsync <= '0';
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90 | end if;
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91 | end if;
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92 |
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93 | if (vertical_counter >= 1) and (vertical_counter <= vga_mode.vertical_sync_pulse_width)
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94 | then
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95 | if vga_mode.vertical_sync_pulse_polarity = neg
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96 | then
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97 | vga_out.vsync <= '0';
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98 | else
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99 | vga_out.vsync <= '1';
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100 | end if;
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101 | else
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102 | if vga_mode.vertical_sync_pulse_polarity = neg
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103 | then
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104 | vga_out.vsync <= '1';
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105 | else
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106 | vga_out.vsync <= '0';
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107 | end if;
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108 | end if;
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109 |
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110 | -- Inkrement horizontal_counter
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111 | horizontal_counter <= horizontal_counter + 1;
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112 | -- Horizontal Sync Sync Pulse Time = 800 Clocks
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113 | if (horizontal_counter = vga_mode.horizontal_sync_pulse_time)
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114 | then
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115 | -- Inkrement vertical_counter
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116 | vertical_counter <= vertical_counter + 1;
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117 | horizontal_counter <= (others => '0');
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118 | end if;
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119 | -- Vertical Sync Sync Pulse Time = 521 Lines
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120 | if (vertical_counter = vga_mode.vertical_sync_pulse_time)
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121 | then
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122 | vertical_counter <= (others => '0');
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123 | end if;
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124 |
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125 | vga_out.hcount <= std_logic_vector(horizontal_counter);
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126 | vga_out.vcount <= std_logic_vector(vertical_counter);
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127 | end if;
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128 | end process;
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129 |
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130 | end architecture rtl;
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131 |
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132 | -----------------------------------------------------------------------------------------------------
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133 |
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134 | library ieee;
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135 | use ieee.std_logic_1164.all;
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136 | use ieee.numeric_std.all;
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137 | use work.vga_control_package.all;
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138 |
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139 | entity vga_controller is
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140 | generic (
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141 | vgamodus : vgamodi := vga480x640at60
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142 | );
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143 | port (
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144 | clock : in std_logic; -- 50 MHz Clock
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145 | vga_out : out vga_out_record
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146 | );
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147 | end vga_controller;
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148 |
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149 | architecture rtl of vga_controller is
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150 |
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151 | component clock25_entity is
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152 | port
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153 | (
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154 | clock50 : in std_logic;
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155 | clock25 : out std_logic
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156 | );
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157 | end component clock25_entity;
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158 |
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159 | component universal_vga_controller is
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160 | port
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161 | (
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162 | clock : in std_logic;
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163 | vga_mode : in vgamode_record;
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164 | vga_out : out vga_out_record
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165 | );
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166 | end component universal_vga_controller;
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167 |
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168 | signal clock25 : std_logic;
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169 | signal vga_mode : vgamode_record;
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170 |
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171 | begin
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172 |
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173 | -- Die If-Anweisung in Verbindung mit generate
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174 | -- ... erfordert ein Label
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175 | label1 : if vgamodus = vga480x640at60 generate
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176 | clock25_port_map : clock25_entity
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177 | port map
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178 | (
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179 | clock50 => clock,
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180 | clock25 => clock25
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181 | );
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182 | end generate;
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183 |
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184 | label2 : if vgamodus = vga480x640at60 generate
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185 | vga_control_port_map : universal_vga_controller
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186 | port map
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187 | (
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188 | clock => clock25, -- 25 MHz Clock
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189 | vga_mode => vga_mode,
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190 | vga_out => vga_out
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191 | );
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192 | end generate;
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193 |
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194 | -- Bei generate kann kein else-Zweig verwendet werden
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195 | -- ... auch keine case-Anweisung
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196 | label3 : if vgamodus = vga600x800at72 generate
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197 | vga_control_port_map : universal_vga_controller
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198 | port map
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199 | (
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200 | clock => clock, -- 50 MHz Clock
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201 | vga_mode => vga_mode,
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202 | vga_out => vga_out
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203 | );
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204 | end generate;
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205 |
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206 | process (clock) is
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207 | begin
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208 | if rising_edge(clock)
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209 | then
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210 | case vgamodus is
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211 | when vga480x640at60 => vga_mode <= vgamode480x640at60;
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212 | when vga600x800at72 => vga_mode <= vgamode600x800at72;
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213 | end case;
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214 | end if;
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215 | end process;
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216 |
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217 | end architecture rtl;
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