Endlich jemand!
Danke Lothar.
ich hab mir das code durch DCM erzugt und in mein VHDL-code eingebunden.
am besten zeige ich dir das code und vielleicht fehlt dir was ein, was
ich falsch gemacht habe:
-------------------------------begin
DCM--------------------------------------------------
GND_BIT <= '0';
CLK0_OUT <= CLKFB_IN;
CLKDV_BUFG_INST : BUFG
port map (I=>CLKDV_BUF,
O=>CLKDV_OUT);
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 10.00,--2.0,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 2,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 30.30,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "HIGH",
DLL_FREQUENCY_MODE => "LOW", --"LOW",
DUTY_CYCLE_CORRECTION => FALSE, -- TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 10,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLOCK, --übergabe 33MHz an DCM CLK input
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>NotReset, --RST_IN,
CLKDV=>CLKDV_BUF,
--CLKFX=>CLKFX_BUF,
CLKFX=>CLK0,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
-------------------------------end
DCM--------------------------------------------------------
Danke!
