[AVR] SPI wartet endlos auf SPIF Flag

Master Mode When the SPI is configured as a master (MSTR in SPCR is set), the user can determine the

direction of the SS pin.

If SS is configured as an output, the pin is a general output pin which does not affect the SPI

system. Typically, the pin will be driving the SS pin of the SPI slave.

If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin

is driven low by peripheral circuitry when the SPI is configured as a master with the SS pin

defined as an input, the SPI system interprets this as another master selecting the SPI as a

slave and starting to send data to it. To avoid bus contention, the SPI system takes the following

actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of the

SPI becoming a slave, the MOSI and SCK pins become inputs.

2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is

set, the interrupt routine will be executed.

Thus, when interrupt-driven SPI transmission is used in master mode, and there exists a possibility

that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the

MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI master

mode.

void SPI_InitMaster()

{

  SPI_DDR |= (1<<SPI_MOSI) | (1<<SPI_SCK) | (1<<SPI_SS);    // outputs

  SPI_DDR &= ~(1<<SPI_MISO);                  // input

  SPI_PORT |= (1<<SPI_MISO);                  // pull-up

  SPCR = (1<<SPE) | (1<<MSTR) | (1<<SPIE);  // enable SPI, Master mode, enable Interrupt

  SPCR = (1<<SPR0 | 1<<SPR1);          // set clock rate /128

}

void SPI_MasterTransmit(uint8_t byte)

{

  SPDR = byte;

  while( !(SPSR & (1<<SPIF)) );  // wait until transmission complete

}