VHDL Xilinx ISE 9.2i 04

Hallo an alle!

ich bekomme folgende Warnung nach der Synthese:

Xst:2677 - Node <Uhf_Samples_0> of sequential type is unconnected in 
block <AdcToplevel_I_AdcDownsample>.
Xst:2677 - Node <Uhf_Samples_1> of sequential type is unconnected in 
block <AdcToplevel_I_AdcDownsample>.
Xst:2677 - Node <Uhf_Samples_2> of sequential type is unconnected in 
block <AdcToplevel_I_AdcDownsample>.
Xst:2677 - Node <Uhf_Samples_3> of sequential type is unconnected in 
block <AdcToplevel_I_AdcDownsample>.

Der passende VHDL Code in meiner Unit "AdcToplevel_I_AdcDownsample" 
sieht so aus:

Uhf_Samples    : out integer range 0 to C_Ringbuffer_length_E
--C_Ringbuffer_length_E = 400
process (SysDataStorEnaOut,RxClk,reset)
variable sample_counter_uhf : integer range 0 to C_Ringbuffer_length_E;
begin
 if (reset='1') then
  sample_counter_uhf := 0;
 elsif rising_edge(SysDataStorEnaOut) then
  if (sample_counter_uhf < C_Ringbuffer_length_E) then
  ...
  sample_counter_uhf := sample_counter_uhf + 1;
  else
   sample_counter_uhf := 0;
  end if;
 end if;
end process;
Uhf_Samples <= sample_counter_uhf;

Also ein Zähler der mehrere Units "rausverdrahtet" wird und in einer 
anderen Unit wieder verwendet wird.

Die oberen Bit (8,7,6,5,4) werden synthetisiert...

Kann mir bitte jm. helfen?

Danke!