Komisches Simulationsergebnis

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity debouncer is

   generic ( reg_width   : natural := 4;   -- how many samples should be stored

             wait_x_clks : natural := 10); -- how many clocks pass between 2 samples

   port ( clk      : in   std_logic;

          sig_in   : in   std_logic;

          sig_out  : out  std_logic);

end debouncer;

architecture rtl of debouncer is

   component mod_x_cnt

      generic ( x : natural := wait_x_clks);

      port ( clk  : in  std_logic;

             rst  : in  std_logic;

             stop : in  std_logic;

             tick : out std_logic);

   end component;

   signal inputsr    : std_logic_vector(reg_width-1 downto 0) := (others => '0');

   signal sample_rdy : std_logic;

begin

   sample_tick : mod_x_cnt

   generic map ( x => wait_x_clks) 

   port map ( clk  => clk,

              rst  => '0',

              stop => '0',

              tick => sample_rdy);

   process 

   begin

      wait until rising_edge(clk);

      if (sample_rdy = '1') then

         if (inputsr = (inputsr'range => '0')) then 

            sig_out <= '0'; 

         end if;

         if (inputsr = (inputsr'range => '1')) then 

            sig_out <= '1';

         end if;         

         inputsr <= inputsr(reg_width-2 downto 0) & sig_in;

      end if;

   end process;

end rtl;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity mod_x_cnt is

   generic ( x : natural := 10);

   port ( clk  : in  std_logic;

          rst  : in  std_logic;

          stop : in  std_logic;

          tick : out std_logic);

end mod_x_cnt;

architecture rtl of mod_x_cnt is

   signal cnt : integer range 0 to x-1 := 0; 

begin

   process

   begin

      wait until rising_edge(clk);

      tick <= '0';

      if (rst = '1') then

         cnt <= 0;

      else

         if (stop = '1') then

            cnt <= cnt;

         else

            if (cnt = (x-1)) then

               cnt <= 0;

               tick <= '1';

            else

               cnt <= cnt + 1;

            end if;

         end if;

      end if;

   end process;

end rtl;

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

ENTITY tb_debouncer IS

END tb_debouncer;

ARCHITECTURE behavior OF tb_debouncer IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT debouncer

    generic ( reg_width   : natural := 4;

              wait_x_clks : natural := 10);

    PORT(

         clk : IN  std_logic;

         sig_in : IN  std_logic;

         sig_out : OUT  std_logic

        );

    END COMPONENT;

   --Inputs

   signal clk : std_logic := '0';

   signal sig_in : std_logic := '0';

   --Outputs

   signal sig_out : std_logic;

   -- Clock period definitions

   constant clk_period : time := 20ns;

BEGIN

  -- Instantiate the Unit Under Test (UUT)

   uut: debouncer

   generic map( reg_width   => 4,

                wait_x_clks => 10)

   PORT MAP (

          clk => clk,

          sig_in => sig_in,

          sig_out => sig_out

        );

   -- Clock process definitions

   clk_process :process

   begin

    clk <= '0';

    wait for clk_period/2;

    clk <= '1';

    wait for clk_period/2;

   end process;

   -- Stimulus process

   stim_proc: process

   begin    

      sig_in <= '1';  wait for clk_period*50;

      sig_in <= '0'; wait for clk_period*5;

      sig_in <= '1'; wait for clk_period*5;

      sig_in <= '0'; wait for clk_period*5;

      sig_in <= '1'; wait for clk_period*5;

      sig_in <= '0'; wait for clk_period*50;

      -- insert stimulus here 

      wait;

   end process;

END;