1 | P3SEL |= 0x06; // Assign I2C pins to USCI_B0
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2 | UCB0CTL1 |= UCSWRST; // Enable SW reset
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3 | UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
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4 | UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset
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5 | UCB0BR0 = 12; // fSCL = SMCLK/12 = ~100kHz
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6 | UCB0BR1 = 0;
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7 | UCB0I2CSA = 88; // Slave Address is 088
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8 | UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
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9 | UCB0IE |= UCTXIE; // Enable TX interrupt
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10 |
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11 | TXByteCtr = sizeof TxData; // Load TX byte counter
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12 |
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13 | while (1)
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14 | {
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15 | __delay_cycles(50); // Delay required between transaction
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16 | PTxData = (unsigned char *)TxData; // TX array start address
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17 | // Place breakpoint here to see each
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18 | // transmit operation.
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19 | UCB0CTL1 |= UCTR + UCTXSTT; // I2C TX, start condition
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20 |
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21 | __bis_SR_register(LPM0_bits + GIE); // Enter LPM0, enable interrupts
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22 | __no_operation(); // Remain in LPM0 until all data
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23 | // is TX'd
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24 | while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
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25 |
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26 |
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27 | #pragma vector = USCI_B0_VECTOR
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28 | __interrupt void USCI_B0_ISR(void)
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29 | {
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30 | switch(__even_in_range(UCB0IV,12))
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31 | {
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32 | case 0: break; // Vector 0: No interrupts
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33 | case 2: break; // Vector 2: ALIFG
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34 | case 4: break; // Vector 4: NACKIFG
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35 | case 6: break; // Vector 6: STTIFG
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36 | case 8: break; // Vector 8: STPIFG
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37 | case 10: break; // Vector 10: RXIFG
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38 | case 12: // Vector 12: TXIFG
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39 | if (TXByteCtr) // Check TX byte counter
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40 | {
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41 | UCB0TXBUF = *PTxData++; // Load TX buffer
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42 | TXByteCtr--; // Decrement TX byte counter
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43 | }
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44 | else
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45 | {
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46 | UCB0CTL1 |= UCTXSTP; // I2C stop condition
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47 | UCB0IFG &= ~UCTXIFG; // Clear USCI_B0 TX int flag
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48 | __bic_SR_register_on_exit(LPM0_bits); // Exit LPM0
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49 | }
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50 | default: break;
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51 | }
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52 | }
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