Hallo an alle, Folgendes Problem: ich versuche eine FSL Verbingung aufzubauen, so sieht das das mhs-file aus: PARAMETER VERSION = 2.1.0 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O PORT fpga_0_DIP_Switches_8Bit_GPIO_in_pin = fpga_0_DIP_Switches_8Bit_GPIO_in, DIR = I, VEC = [0:7] PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT, DIR = O PORT fpga_0_DDR2_SDRAM_DDR2_Addr_pin = fpga_0_DDR2_SDRAM_DDR2_Addr, DIR = O, VEC = [12:0] PORT fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin = fpga_0_DDR2_SDRAM_DDR2_BankAddr, DIR = O, VEC = [1:0] PORT fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_n, DIR = O PORT fpga_0_DDR2_SDRAM_DDR2_CE_pin = fpga_0_DDR2_SDRAM_DDR2_CE, DIR = O PORT fpga_0_DDR2_SDRAM_DDR2_CS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CS_n, DIR = O PORT fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_n, DIR = O PORT fpga_0_DDR2_SDRAM_DDR2_WE_n_pin = fpga_0_DDR2_SDRAM_DDR2_WE_n, DIR = O PORT fpga_0_DDR2_SDRAM_DDR2_Clk_pin = fpga_0_DDR2_SDRAM_DDR2_Clk, DIR = O, VEC = [1:0] PORT fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin = fpga_0_DDR2_SDRAM_DDR2_Clk_n, DIR = O, VEC = [1:0] PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM, DIR = O, VEC = [3:0] PORT fpga_0_DDR2_SDRAM_DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS, DIR = IO, VEC = [3:0] PORT fpga_0_DDR2_SDRAM_DDR2_DQS_n = fpga_0_DDR2_SDRAM_DDR2_DQS_n, DIR = IO, VEC = [3:0] PORT fpga_0_DDR2_SDRAM_DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ, DIR = IO, VEC = [31:0] PORT fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I, DIR = I PORT fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O, DIR = O PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A, DIR = O, VEC = [8:31] PORT fpga_0_FLASH_Mem_DQ_pin = fpga_0_FLASH_Mem_DQ, DIR = IO, VEC = [0:7] PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN, DIR = O PORT fpga_0_FLASH_Mem_RPN_pin = fpga_0_FLASH_Mem_RPN, DIR = O PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN, DIR = O PORT fpga_0_FLASH_Mem_CEN_pin = fpga_0_FLASH_Mem_CEN, DIR = O PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST PORT eigener_ip_0_LEDOUT_pin = eigener_ip_0_LEDOUT, DIR = O, VEC = [1:0] BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 7.10.a PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_AREA_OPTIMIZED = 1 PARAMETER C_FSL_LINKS = 1 PARAMETER C_FAMILY = spartan3adsp PARAMETER C_INSTANCE = microblaze_0 BUS_INTERFACE DPLB = mb_plb BUS_INTERFACE IPLB = mb_plb BUS_INTERFACE DEBUG = microblaze_0_dbg BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE MFSL0 = fsl_v20_0 PORT MB_RESET = mb_reset END BEGIN plb_v46 PARAMETER INSTANCE = mb_plb PARAMETER HW_VER = 1.02.a PORT PLB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_port END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_port END BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = ilmb_port BUS_INTERFACE PORTB = dlmb_port END BEGIN xps_uartlite PARAMETER INSTANCE = RS232_Uart_1 PARAMETER HW_VER = 1.00.a PARAMETER C_BAUDRATE = 9600 PARAMETER C_DATA_BITS = 8 PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_SPLB_CLK_FREQ_HZ = 62500000 PARAMETER C_BASEADDR = 0x84000000 PARAMETER C_HIGHADDR = 0x8400ffff BUS_INTERFACE SPLB = mb_plb PORT RX = fpga_0_RS232_Uart_1_RX PORT TX = fpga_0_RS232_Uart_1_TX END BEGIN xps_gpio PARAMETER INSTANCE = DIP_Switches_8Bit PARAMETER HW_VER = 1.00.a PARAMETER C_GPIO_WIDTH = 8 PARAMETER C_IS_DUAL = 0 PARAMETER C_IS_BIDIR = 0 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_BASEADDR = 0x81400000 PARAMETER C_HIGHADDR = 0x8140ffff BUS_INTERFACE SPLB = mb_plb PORT GPIO_in = fpga_0_DIP_Switches_8Bit_GPIO_in END BEGIN mpmc PARAMETER INSTANCE = DDR2_SDRAM PARAMETER HW_VER = 4.00.a PARAMETER C_NUM_PORTS = 1 PARAMETER C_MEM_PARTNO = MT47H32M16-5E PARAMETER C_DDR2_DQSN_ENABLE = 1 PARAMETER C_MEM_DATA_WIDTH = 32 PARAMETER C_MEM_CLK_WIDTH = 2 PARAMETER C_MEM_DM_WIDTH = 4 PARAMETER C_MEM_DQS_WIDTH = 4 PARAMETER C_PIM0_BASETYPE = 2 PARAMETER C_MPMC_CLK0_PERIOD_PS = 8000 PARAMETER C_MPMC_BASEADDR = 0x88000000 PARAMETER C_MPMC_HIGHADDR = 0x8fffffff BUS_INTERFACE SPLB0 = mb_plb PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT PORT DDR2_Addr = fpga_0_DDR2_SDRAM_DDR2_Addr PORT DDR2_BankAddr = fpga_0_DDR2_SDRAM_DDR2_BankAddr PORT DDR2_CAS_n = fpga_0_DDR2_SDRAM_DDR2_CAS_n PORT DDR2_CE = fpga_0_DDR2_SDRAM_DDR2_CE PORT DDR2_CS_n = fpga_0_DDR2_SDRAM_DDR2_CS_n PORT DDR2_RAS_n = fpga_0_DDR2_SDRAM_DDR2_RAS_n PORT DDR2_WE_n = fpga_0_DDR2_SDRAM_DDR2_WE_n PORT DDR2_Clk = fpga_0_DDR2_SDRAM_DDR2_Clk PORT DDR2_Clk_n = fpga_0_DDR2_SDRAM_DDR2_Clk_n PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS PORT DDR2_DQS_n = fpga_0_DDR2_SDRAM_DDR2_DQS_n PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ PORT DDR2_DQS_Div_I = fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I PORT DDR2_DQS_Div_O = fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O PORT MPMC_Clk0 = DDR2_SDRAM_mpmc_clk_s PORT MPMC_Clk90 = DDR2_SDRAM_mpmc_clk_90_s PORT MPMC_Rst = sys_periph_reset END BEGIN xps_mch_emc PARAMETER INSTANCE = FLASH PARAMETER HW_VER = 1.00.a PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 16000 PARAMETER C_NUM_BANKS_MEM = 1 PARAMETER C_MAX_MEM_WIDTH = 8 PARAMETER C_MEM0_WIDTH = 8 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1 PARAMETER C_SYNCH_MEM_0 = 0 PARAMETER C_TCEDV_PS_MEM_0 = 70000 PARAMETER C_TAVDV_PS_MEM_0 = 70000 PARAMETER C_TWC_PS_MEM_0 = 70000 PARAMETER C_TWP_PS_MEM_0 = 45000 PARAMETER C_THZOE_PS_MEM_0 = 25000 PARAMETER C_THZCE_PS_MEM_0 = 25000 PARAMETER C_TLZWE_PS_MEM_0 = 5000 PARAMETER C_MEM0_BASEADDR = 0x87000000 PARAMETER C_MEM0_HIGHADDR = 0x87ffffff BUS_INTERFACE SPLB = mb_plb PORT Mem_A = fpga_0_FLASH_Mem_A_split PORT Mem_WEN = fpga_0_FLASH_Mem_WEN PORT Mem_DQ = fpga_0_FLASH_Mem_DQ PORT Mem_OEN = fpga_0_FLASH_Mem_OEN PORT Mem_CEN = fpga_0_FLASH_Mem_CEN PORT Mem_RPN = fpga_0_FLASH_Mem_RPN END BEGIN util_bus_split PARAMETER INSTANCE = FLASH_util_bus_split_1 PARAMETER HW_VER = 1.00.a PARAMETER C_SIZE_IN = 32 PARAMETER C_LEFT_POS = 0 PARAMETER C_SPLIT = 8 PORT Sig = fpga_0_FLASH_Mem_A_split PORT Out2 = fpga_0_FLASH_Mem_A END BEGIN clock_generator PARAMETER INSTANCE = clock_generator_0 PARAMETER HW_VER = 2.00.a PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER C_CLKIN_FREQ = 125000000 PARAMETER C_CLKOUT0_FREQ = 62500000 PARAMETER C_CLKOUT0_BUF = TRUE PARAMETER C_CLKOUT0_PHASE = 0 PARAMETER C_CLKOUT0_GROUP = NONE PARAMETER C_CLKOUT1_FREQ = 125000000 PARAMETER C_CLKOUT1_BUF = TRUE PARAMETER C_CLKOUT1_PHASE = 0 PARAMETER C_CLKOUT1_GROUP = DCM0 PARAMETER C_CLKOUT2_FREQ = 125000000 PARAMETER C_CLKOUT2_BUF = TRUE PARAMETER C_CLKOUT2_PHASE = 90 PARAMETER C_CLKOUT2_GROUP = DCM0 PORT CLKOUT0 = sys_clk_s PORT CLKOUT1 = DDR2_SDRAM_mpmc_clk_s PORT CLKOUT2 = DDR2_SDRAM_mpmc_clk_90_s PORT CLKIN = dcm_clk_s PORT LOCKED = Dcm_all_locked PORT RST = net_gnd END BEGIN mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 1.00.b PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_BASEADDR = 0x84400000 PARAMETER C_HIGHADDR = 0x8440ffff BUS_INTERFACE SPLB = mb_plb BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg PORT Debug_SYS_Rst = Debug_SYS_Rst END BEGIN proc_sys_reset PARAMETER INSTANCE = proc_sys_reset_0 PARAMETER HW_VER = 2.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT Slowest_sync_clk = sys_clk_s PORT Dcm_locked = Dcm_all_locked PORT Ext_Reset_In = sys_rst_s PORT MB_Reset = mb_reset PORT Bus_Struct_Reset = sys_bus_reset PORT MB_Debug_Sys_Rst = Debug_SYS_Rst PORT Peripheral_Reset = sys_periph_reset END BEGIN eigener_ip PARAMETER INSTANCE = eigener_ip_0 PARAMETER HW_VER = 1.00.a BUS_INTERFACE SFSL = fsl_v20_0 PORT LEDOUT = eigener_ip_0_LEDOUT END BEGIN fsl_v20 PARAMETER INSTANCE = fsl_v20_0 PARAMETER HW_VER = 2.11.a PARAMETER C_EXT_RESET_HIGH = 0 PORT FSL_Clk = sys_clk_s PORT SYS_Rst = sys_rst_s PORT FSL_M_Clk = net_gnd PORT FSL_S_Clk = net_gnd END ---------- --------- Beim Download bekomme ich dann folgende Fehlermeldung: ERROR:Portability:89 - File system full Davor habe ich das System schon mehrmals ins FPGA geladen,... ohne Fehler Auf welche Einstellungen sollte man beim FSL Aufbau achten, ... und wie überprüft man am besten ob diese auch richtig im FPGA funktioniert? Danke im Voraus Peter
> Auf welche Einstellungen sollte man beim FSL Aufbau achten...
Darauf, dass auf der Festplatte noch genügend Platz für die Unmengen von
Dateien ist, die so ein EDK-Lauf erzeugt?
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