Quartus II Clock

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity ioctrl is

  port (clk48    : in    std_logic;                     -- 48 MHz system clock 

        reset_n  : in    std_logic;                     -- asynchronous reset

        led      : out   std_logic_vector(6 downto 0);

        led2     : out   std_logic); 

end ioctrl;

architecture rtl of ioctrl is

  constant C_ENCOUNTVAL : std_logic_vector(14 downto 0):= "100101100000000";

  --signal s_busfsm  : t_busfsm;

  --signal s_enctr   : std_logic_vector(14 downto 0);

  --signal s_10khzen : std_logic;

  signal s_led       : std_logic_vector(7 downto 0);

begin  -- rtl

  -----------------------------------------------------------------------------

  --

  -- Generate 10 KHz enable signal.

  --

  -----------------------------------------------------------------------------

  --p_slowen: process (clk48, reset_n)

  --begin  -- process p_slowen

  --  if reset_n = '0' then                   -- asynchronous reset (active low)

  --    s_10khzen <= '0';

  --    s_enctr <= (others => '0');

  --  elsif clk48'event and clk48 = '1' then  -- rising clock edge

  --    -- Enable signal is inactive per default.

  --    s_10khzen <= '0';

  --    if s_enctr /= C_ENCOUNTVAL then

  --      -- As long as the terminal count is not reached: increment the counter.

  --     s_enctr <= unsigned(s_enctr) + conv_unsigned(1,1);

  --    else

        -- When the terminal count is reached, set enable flag and reset the

        -- counter.

  --      s_enctr <= (others => '0');

  --      s_10khzen <= '1';

  --    end if;

  --  end if;

  --end process p_slowen;

  -----------------------------------------------------------------------------

  --

  -- Generate state machine to put out and to read in data from the bus in a

  -- loop.

  --

  -----------------------------------------------------------------------------

  p_busfsm: process (clk48, reset_n)

  begin  -- process p_busfsm

    if reset_n = '0' then                   -- asynchronous reset (active low)

      s_led <= "10000001";

    elsif clk48'event and clk48 = '1' then  -- rising clock edge

      --if s_10khzen = '1' then

        s_led <= "11110000";--not s_led;

      --end if;

    end if;

  end process p_busfsm;

led <= s_led(6 downto 0);

led2<= s_led(7);

end rtl;