Hallo, ich versuche gerade eine FSM zu erstellen, sie bekommt Daten über ein SPI interface und je nachdem welches Kommando kam wir dann halt was gemacht. Im RTL wird allerdings nirgends eine FSM angezeigt. :( Programmiert wird in Xilinx ISE 11.1 (Gekürzte Version):
1 | library IEEE; |
2 | use IEEE.STD_LOGIC_1164.ALL; |
3 | use IEEE.STD_LOGIC_ARITH.ALL; |
4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
5 | |
6 | ---- Uncomment the following library declaration if instantiating
|
7 | ---- any Xilinx primitives in this code.
|
8 | --library UNISIM;
|
9 | --use UNISIM.VComponents.all;
|
10 | |
11 | entity Controller is |
12 | Port ( MCLK : in STD_LOGIC; --Master Clock Input |
13 | Din : in STD_LOGIC_VECTOR (7 downto 0); --Data from SPI |
14 | Dout : out STD_LOGIC_VECTOR (7 downto 0); --Data to SPI |
15 | SlaveSel : in STD_LOGIC; --SPI Slave Selected (1: is selected) |
16 | DRDY : in STD_LOGIC; --New Data from SPI Slave Controller |
17 | DRDY_CLR : out STD_LOGIC; --Clear the new Data indicator of SPI Slave |
18 | MatrixOut : out STD_LOGIC_VECTOR (63 downto 0); --Desired Output of the LED-Matrix |
19 | KeyChange : in STD_LOGIC_VECTOR (7 downto 0); --Which Key of Key-Matrix has Changed? |
20 | SSG1 : out STD_LOGIC_VECTOR (7 downto 0); --Output Val for 1st 7-Segment Display (7th Bit->LED) |
21 | SSG2 : out STD_LOGIC_VECTOR (7 downto 0)); --Output Val for 2nd 7-Segment Display (7th Bit->LED) |
22 | end Controller; |
23 | |
24 | architecture Behavioral of Controller is |
25 | type state_t is ( Idle, |
26 | SPIDecode, |
27 | SPIWaitForData, |
28 | LEDMtrStR0, |
29 | LEDMtrStR1, |
30 | LEDMtrStR2, |
31 | LEDMtrStR3, |
32 | LEDMtrStR4, |
33 | LEDMtrStR5, |
34 | LEDMtrStR6, |
35 | LEDMtrStR7, |
36 | WaitForRst); |
37 | signal state, SANS : state_t := idle; --SANS: State after next State |
38 | |
39 | begin
|
40 | |
41 | Ctrl_FSM: process(MCLK, SlaveSel) |
42 | begin
|
43 | |
44 | if (SlaveSel='0') then |
45 | state <= Idle; |
46 | |
47 | elsif rising_edge(MCLK) then |
48 | case state is |
49 | when Idle => if DRDY='1' then |
50 | state <= SPIDecode; |
51 | DRDY_CLR <= '1'; |
52 | end if; |
53 | |
54 | when SPIDecode => |
55 | DRDY_CLR <= '0'; |
56 | if Din="10000000" then |
57 | SANS <= LEDMtrStR0; |
58 | state <= SPIWaitForData; |
59 | |
60 | elsif Din="10000001" then |
61 | SANS <= LEDMtrStR1; |
62 | state <= SPIWaitForData; |
63 | |
64 | else
|
65 | state <= WaitForRst; --if SPI-OpCode is unknown wait until SlaveSel toggle |
66 | end if; |
67 | |
68 | when SPIWaitForData => |
69 | if DRDY='1' then |
70 | |
71 | DRDY_CLR <= '1'; |
72 | state <= SANS; |
73 | end if; |
74 | |
75 | when LEDMtrStR0 => |
76 | DRDY_CLR <= '0'; |
77 | MatrixOut(7 downto 0) <= Din; |
78 | state <= Idle; |
79 | |
80 | when LEDMtrStR1 => |
81 | DRDY_CLR <= '0'; |
82 | MatrixOut(15 downto 8) <= Din; |
83 | state <= Idle; |
84 | |
85 | |
86 | when WaitForRst => |
87 | state <= WaitForRst; --waits until state is set to idle from SlaveSel='0' |
88 | |
89 | end case; |
90 | end if; |
91 | end process Ctrl_FSM; |
92 | |
93 | end Behavioral; |
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