ISE erkennt FSM nicht

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Controller is

    Port ( MCLK : in STD_LOGIC;                    --Master Clock Input

        Din : in  STD_LOGIC_VECTOR (7 downto 0);      --Data from SPI

           Dout : out  STD_LOGIC_VECTOR (7 downto 0);      --Data to SPI

           SlaveSel : in  STD_LOGIC;                --SPI Slave Selected (1: is selected)

           DRDY : in  STD_LOGIC;                    --New Data from SPI Slave Controller

           DRDY_CLR : out  STD_LOGIC;                --Clear the new Data indicator of SPI Slave

           MatrixOut : out  STD_LOGIC_VECTOR (63 downto 0);  --Desired Output of the LED-Matrix

           KeyChange : in  STD_LOGIC_VECTOR (7 downto 0);  --Which Key of Key-Matrix has Changed?

           SSG1 : out  STD_LOGIC_VECTOR (7 downto 0);      --Output Val for 1st 7-Segment Display (7th Bit->LED)

           SSG2 : out  STD_LOGIC_VECTOR (7 downto 0));    --Output Val for 2nd 7-Segment Display (7th Bit->LED)

end Controller;

architecture Behavioral of Controller is

  type state_t is (  Idle, 

              SPIDecode,

              SPIWaitForData, 

              LEDMtrStR0, 

              LEDMtrStR1, 

              LEDMtrStR2, 

              LEDMtrStR3, 

              LEDMtrStR4, 

              LEDMtrStR5, 

              LEDMtrStR6, 

              LEDMtrStR7, 

              WaitForRst);

  signal state, SANS : state_t := idle;              --SANS: State after next State

  begin

     Ctrl_FSM: process(MCLK, SlaveSel)

    begin

    if (SlaveSel='0') then

         state <= Idle;

      elsif rising_edge(MCLK) then

       case state is

         when Idle =>     if DRDY='1' then 

                    state <= SPIDecode;

                    DRDY_CLR <= '1';

                  end if;

         when SPIDecode => 

                  DRDY_CLR <= '0';

                  if Din="10000000" then

                    SANS <= LEDMtrStR0;

                    state <= SPIWaitForData;

                    elsif Din="10000001" then

                    SANS <= LEDMtrStR1;

                    state <= SPIWaitForData;

                  else

                    state <= WaitForRst;  --if SPI-OpCode is unknown wait until SlaveSel toggle

                  end if;

       when SPIWaitForData => 

                  if DRDY='1' then 

                    DRDY_CLR <= '1';

                    state <= SANS;

                  end if;

         when LEDMtrStR0 =>

                  DRDY_CLR <= '0';

                  MatrixOut(7 downto 0) <= Din;

                  state <= Idle;

      when LEDMtrStR1 =>

                  DRDY_CLR <= '0';

                  MatrixOut(15 downto 8) <= Din;

                  state <= Idle;

      when WaitForRst =>

                  state <= WaitForRst; --waits until state is set to idle from SlaveSel='0'

       end case;

      end if;

   end process Ctrl_FSM;

  end Behavioral;