1 | ;**** T I T L E R C 5 T I N Y L A M P ***************************************
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2 |
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3 | ;*
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4 |
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5 | ;* Title :RC5TinyLamp
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6 |
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7 | ;* Version :1.0
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8 |
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9 | ;* Date :00.05.31
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10 |
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11 | ;* Last updated :00.08.19
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12 |
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13 | ;* Target :ATTiny22
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14 |
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15 | ;* Crystal frequency :1Mhz intern oscillator
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16 |
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17 | ;*
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18 |
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19 | ;* Support :J.v.Boxtel
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20 |
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21 | ;* Support E-mail :boxteldoelen@hetnet.nl
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22 |
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23 | ;*
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24 |
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25 | ;* Code Size :149 words
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26 |
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27 | ;* Low Register Usage :5
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28 |
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29 | ;* High Register Usage :11
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30 |
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31 | ;* Interrupt Usage :
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32 |
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33 | ;* Based on :avr410 rc5, avr100 EEprom access, RC5Lamp
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34 |
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35 | ;*
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36 |
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37 | ;* DESCRIPTION
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38 |
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39 | ;* This Application switch a lamp on/off with RC5 if
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40 |
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41 | ;* system and lamp_nr are correct
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42 |
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43 | ;* system and lamp_nr are can be change with the "learn_button"
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44 |
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45 | ;* pB2 (pin7) is IRinput, pB3 (pin2) is learn button, pB0 (pin5) is output
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46 |
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47 | ;* pB3 learbutton open=normal groud=learn
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48 |
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49 | ;* pB1 (pin6) ext interrupt
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50 |
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51 | ;***************************************************************************
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52 |
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53 |
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54 |
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55 | .include "c:\avrtools\appnotes\tn22def.inc"
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56 |
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57 |
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58 |
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59 | .equ INPUT =2 ;PB2 input for ir reciever
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60 |
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61 |
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62 |
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63 | .def S =R0 ;Storage for the Status Register
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64 |
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65 | .def inttemp =R1 ;Temporary variable for ISR
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66 |
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67 | .def ref1 =R2 ;Reference for timing
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68 |
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69 | .def ref2 =R3 ;Reference for timing
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70 |
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71 | .def EEdrd =R4 ;read data byte from EEprom
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72 |
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73 | .def temp =R16 ;Temporary variable
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74 |
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75 | .def timerL =R17 ;Timing variable updated every 14 us
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76 |
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77 | .def timerH =R18 ;Timing variable updated every 16 ms
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78 |
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79 | .def system =R19 ;Address data received
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80 |
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81 | .def command =R20 ;Command received
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82 |
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83 | .def bitcnt =R21 ;Counter
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84 |
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85 | .def SYS_ADDR =R22 ;Systen addres to respond on
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86 |
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87 | .def LAMP_NR =R23 ;Lamp number to respond on
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88 |
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89 | .def EEard =R24 ;address to read from
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90 |
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91 | .def EEdwr =R25 ;data byte to write to EEPROM
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92 |
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93 | .def EEawr =R26 ;address byte to write to
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94 |
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95 | .def tim1 =R27
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96 |
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97 | .def tim2 =R28
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98 |
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99 | .equ zeit =255
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100 |
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101 |
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102 |
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103 | .cseg
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104 |
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105 | .org 0
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106 |
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107 |
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108 |
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109 | rjmp reset
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110 |
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111 |
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112 |
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113 | ;********************************************************************
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114 |
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115 | ;* "TIM0_OVF" - Timer/counter overflow interrupt handler
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116 |
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117 | ;*
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118 |
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119 | ;* The overflow interrupt increments the "timerL" and "timerH"
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120 |
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121 | ;* every 64us and 16,384us.
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122 |
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123 | ;*
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124 |
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125 | ;* Crystal Frequency is 1 MHz
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126 |
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127 | ;*
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128 |
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129 | ;* Number of words:
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130 |
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131 | ;* Number of cycles:6 + reti
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132 |
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133 | ;* Low registers used:1
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134 |
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135 | ;* High registers used: 3
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136 |
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137 | ;* Pointers used:0
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138 |
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139 | ;********************************************************************
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140 |
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141 | .org OVF0addr
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142 |
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143 | TIM0_OVF:
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144 |
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145 | in S,sreg ; Store SREG
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146 |
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147 | inc timerL ; Updated every 64us
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148 |
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149 | inc inttemp ; 4 MHz clock
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150 |
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151 | inc timerL ; Updated every 64us
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152 |
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153 | inc inttemp ; 3 MHz clock
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154 |
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155 | inc timerL ; Updated every 64us
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156 |
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157 | inc inttemp ; 2 MHz clock
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158 |
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159 | inc timerL ; Updated every 64us
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160 |
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161 | inc inttemp ; 1 MHz clock
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162 |
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163 | brne TIM0_OVF_exit
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164 |
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165 |
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166 |
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167 | inc timerH ; if 256th int inc timer
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168 |
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169 |
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170 |
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171 | TIM0_OVF_exit:
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172 |
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173 | out sreg,S ; Restore SREG
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174 |
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175 | reti
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176 |
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177 |
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178 |
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179 | reset:
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180 |
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181 | ldi temp,1 ;Timer/Counter 0 clocked at CK
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182 |
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183 | out TCCR0,temp ; Timer counter 0 prescaler
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184 |
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185 | ldi temp,1<<TOIE0 ;Enable Timer0 overflow interrupt
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186 |
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187 | out TIMSK,temp ; set timer interrupt mask
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188 |
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189 | ldi temp,0x01 ;PORTB 0 as output
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190 |
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191 | out DDRb,temp ; set direction
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192 |
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193 | ldi temp,15 ;load 15 for init pullup on pB1,pB2;pB3
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194 |
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195 | out portb,temp ; and set defaul lamp off after reset
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196 |
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197 |
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198 |
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199 | ldi temp,ramend ;init stack pointer
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200 |
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201 | out spl,temp ; ram_end to spl
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202 |
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203 |
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204 |
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205 | sei ;Enable global interrupt
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206 |
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207 | cbi $18,0
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208 |
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209 |
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210 |
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211 | main:
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212 |
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213 | rcall detect ;Call RC5 detect routine
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214 |
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215 |
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216 |
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217 | cpi command,0xFF ;If no or wrong code return to main
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218 |
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219 | breq main
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220 |
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221 |
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222 |
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223 | in temp,pinb ;learbutton test
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224 |
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225 | andi temp,$08 ; test pb3 only (learnbutton)
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226 |
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227 | cpi temp,$08 ; high then main1
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228 |
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229 | breq main1
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230 |
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231 |
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232 |
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233 |
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234 |
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235 | mov EEdwr,system ;store new system addres in EEprom
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236 |
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237 | ldi EEawr,$00 ; at addres 00
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238 |
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239 | rcall EEWrite ; store system in EEPROM location $0000
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240 |
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241 |
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242 |
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243 | andi command,0x3F ;remove toggle bit
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244 |
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245 | mov EEdwr,command ;store new command in EEprom
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246 |
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247 | ldi EEawr,$01 ; at addres $0001
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248 |
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249 | rcall EEWrite ; store command in EEPROM location $0001
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250 |
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251 |
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252 |
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253 | main1:
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254 |
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255 | rcall readin ;readin the system-addres and lamp_nr
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256 |
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257 |
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258 |
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259 | cp system,sys_addr ;correct addres? else return to main
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260 |
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261 | brne main
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262 |
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263 |
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264 |
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265 | andi command,0x3F ;remove toggle bit
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266 |
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267 | cp command,lamp_nr ;correct lamp nr? else return to main
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268 |
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269 | brne main
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270 |
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271 | invert:
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272 |
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273 | brts invert1 ;if T bit is 0 then lamp on
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274 |
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275 | set ;set t bit (lamp on code)
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276 |
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277 | cbi $18,0 ;port pin low =lamp on
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278 |
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279 | rjmp wait
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280 |
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281 | invert1: ;if t bit is 1 then lamp off
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282 |
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283 | sbi $18,0 ;set pin high
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284 |
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285 | rcall pause ;Pause
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286 |
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287 | rcall pause ;Pause
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288 |
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289 | cbi $18,0 ;set pin low
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290 |
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291 | wait:
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292 |
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293 | rcall detect ;Call RC5 detect routine and
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294 |
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295 | cpi command,0xFF ; wait until button is released
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296 |
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297 | brne wait ;
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298 |
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299 | rjmp main ;
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300 |
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301 |
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302 |
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303 | readin:
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304 |
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305 | ldi EEard,$00 ;load addres
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306 |
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307 | rcall EERead ;read address $00 (System addres)
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308 |
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309 | mov sys_addr,EEdrd ;load system addres
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310 |
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311 |
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312 |
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313 | ldi EEard,$01 ;load addres
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314 |
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315 | rcall EERead ;read address $01 (command number)
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316 |
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317 | mov lamp_nr,EEdrd ;command mumber is lamp number
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318 |
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319 |
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320 |
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321 | ret
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322 |
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323 |
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324 |
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325 | ;***************************************************************************
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326 |
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327 | ;*
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328 |
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329 | ;* EERead
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330 |
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331 | ;*
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332 |
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333 | ;* This subroutine waits until the EEPROM is ready to be programmed, then
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334 |
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335 | ;* reads the register variable "EEdrd" from address "EEardh:EEard"
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336 |
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337 | ;*
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338 |
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339 | ;* Number of words :1200 ; 5 + return
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340 |
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341 | ;* :8515 ; 6 + return
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342 |
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343 | ;* Number of cycles :1200 ; 8 + return (if EEPROM is ready)
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344 |
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345 | ;* :8515 ; 9 + return (if EEPROM is ready)
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346 |
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347 | ;* Low Registers used :1 (EEdrd)
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348 |
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349 | ;* High Registers used: :2 (EEard,EEardh)
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350 |
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351 | ;*
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352 |
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353 | ;***************************************************************************
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354 |
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355 |
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356 |
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357 |
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358 |
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359 | EERead:
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360 |
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361 | sbic EECR,EEWE ;if EEWE not clear
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362 |
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363 | rjmp EERead ; wait more
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364 |
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365 | out EEAR,EEard ;output address for 1200
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366 |
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367 |
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368 |
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369 |
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370 |
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371 | sbi EECR,EERE ;set EEPROM Read strobe
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372 |
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373 | ;This instruction takes 4 clock cycles since
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374 |
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375 | ;it halts the CPU for two clock cycles
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376 |
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377 | in EEdrd,EEDR ;get data
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378 |
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379 | ret
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380 |
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381 |
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382 |
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383 | EEWrite:
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384 |
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385 | sbic EECR,EEWE ;if EEWE not clear
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386 |
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387 | rjmp EEWrite ; wait more
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388 |
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389 |
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390 |
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391 | out EEARL,EEawr ;output address low
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392 |
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393 |
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394 |
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395 | out EEDR,EEdwr ;output data
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396 |
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397 | sbi EECR,EEMWE ; set master write enable
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398 |
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399 | sbi EECR,EEWE ; set EEPROM Write strobe
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400 |
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401 | ; This instruction takes 4 clock cycles since
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402 |
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403 | ; it halts the CPU for two clock cycles
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404 |
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405 | ret
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406 |
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407 |
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408 |
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409 | pause1:
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410 |
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411 | ldi tim2,zeit ;Lade Wert in Register
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412 |
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413 | s2:
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414 |
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415 | dec tim2 ;tim2 - 1
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416 |
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417 | brne s2 ;Wenn tim2 > 0 dann springe nach s1
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418 |
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419 | ret
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420 |
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421 |
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422 |
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423 | pause:
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424 |
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425 | ldi tim1,zeit ;Lade Wert in Register
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426 |
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427 | s1:
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428 |
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429 | rcall pause1 ;Rufe Schleife1 auf
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430 |
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431 | dec tim1 ;tim1 - 1
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432 |
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433 | brne s1 ;Wenn tim1 > 0 dann springe nach s1
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434 |
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435 | ret
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436 |
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437 |
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438 |
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439 | ;********************************************************************
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440 |
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441 | ;* "detect" - RC5 decode routine
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442 |
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443 | ;*
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444 |
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445 | ;* This subroutine decodes the RC5 bit stream applied on PORTB
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446 |
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447 | ;* pin "INPUT".
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448 |
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449 | ;*
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450 |
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451 | ;* If success: The command and system address are
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452 |
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453 | ;* returned in "command" and "system".
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454 |
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455 | ;* Bit 6 of "command" holds the toggle bit.
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456 |
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457 | ;*
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458 |
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459 | ;* If failed: $FF in both "system" and "command"
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460 |
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461 | ;*
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462 |
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463 | ;* Crystal frequency is 4MHz
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464 |
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465 | ;*
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466 |
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467 | ;* Number of words:72
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468 |
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469 | ;* Low registers used: 3
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470 |
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471 | ;* High registers used: 6
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472 |
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473 | ;* Pointers used: 0
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474 |
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475 | ;********************************************************************
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476 |
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477 | detect0: ;only for test
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478 |
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479 | ldi command,0x7
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480 |
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481 | ldi system,0x05
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482 |
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483 | ret
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484 |
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485 |
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486 |
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487 | detect:
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488 |
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489 | clr inttemp ; Init Counters
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490 |
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491 | clr timerH
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492 |
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493 | detect1:
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494 |
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495 | clr timerL
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496 |
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497 | detect2:
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498 |
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499 | cpi timerH,8 ;If line not idle within 131ms
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500 |
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501 | brlo dl1
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502 |
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503 | rjmp fault ;then exit
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504 |
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505 | dl1:
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506 |
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507 | cpi timerL,55 ;If line low for 3.5ms
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508 |
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509 | brge start1 ;then wait for start bit
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510 |
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511 | sbis PINB,INPUT ;If line is
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512 |
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513 | rjmp detect1 ;low - jump to detect1
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514 |
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515 | rjmp detect2 ;high - jump to detect2
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516 |
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517 | start1:
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518 |
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519 | cpi timerH,8 ;If no start bit detected
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520 |
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521 | brge fault ;within 130ms then exit
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522 |
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523 | sbic PINB,INPUT ;Wait for start bit
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524 |
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525 | rjmp start1
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526 |
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527 | clr timerL ;Measure length of start bit
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528 |
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529 | start2:
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530 |
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531 | cpi timerL,17 ;If startbit longer than 1.1ms,
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532 |
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533 | brge fault ;exit
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534 |
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535 | sbis PINB,INPUT
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536 |
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537 | rjmp start2 ;Positive edge of 1st start bit
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538 |
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539 | mov temp,timerL ;timer is 1/2 bit time.
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540 |
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541 |
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542 |
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543 | clr timerL
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544 |
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545 | mov ref1,temp
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546 |
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547 | lsr ref1
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548 |
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549 | mov ref2,ref1
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550 |
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551 | add ref1,temp ;ref1 = 3/4 bit time
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552 |
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553 | lsl temp
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554 |
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555 | add ref2,temp ;ref2 = 5/4 bit time
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556 |
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557 | start3:
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558 |
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559 | cp timerL,ref1 ;If high period St2 > 3/4 bit time
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560 |
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561 | brge fault ;exit
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562 |
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563 | sbic PINB,INPUT ;Wait for falling edge start bit 2
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564 |
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565 | rjmp start3
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566 |
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567 | clr timerL
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568 |
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569 | ldi bitcnt,12 ;Receive 12 bits
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570 |
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571 | clr command
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572 |
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573 | clr system
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574 |
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575 | sample:
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576 |
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577 | cp timerL,ref1 ;Sample INPUT at 1/4 bit time
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578 |
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579 | brlo sample
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580 |
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581 | sbic PINB,INPUT
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582 |
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583 | rjmp bit_is_a_1 ;Jump if line high
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584 |
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585 | bit_is_a_0:
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586 |
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587 | clc ;Store a 0
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588 |
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589 | rol command
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590 |
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591 | rol system
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592 |
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593 | ;Synchronize timing
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594 |
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595 | bit_is_a_0a:
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596 |
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597 | cp timerL,ref2 ;If no edge within 3/4 bit time
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598 |
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599 | brge fault ;exit
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600 |
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601 | sbis PINB,INPUT ;Wait for rising edge
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602 |
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603 | rjmp bit_is_a_0a ;in the middle of the bit
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604 |
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605 | clr timerL
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606 |
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607 | rjmp nextbit
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608 |
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609 | bit_is_a_1:
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610 |
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611 | sec ;Store a 1
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612 |
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613 | rol command
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614 |
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615 | rol system
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616 |
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617 | ;Synchronize timing
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618 |
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619 | bit_is_a_1a:
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620 |
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621 | cp timerL,ref2 ;If no edge within 3/4 bit time
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622 |
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623 | brge fault ;exit
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624 |
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625 | sbic PINB,INPUT ;Wait for falling edge
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626 |
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627 | rjmp bit_is_a_1a ;in the middle of the bit.
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628 |
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629 | clr timerL
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630 |
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631 | nextbit:
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632 |
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633 | dec bitcnt ;If bitcnt > 0
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634 |
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635 | brne sample ;get next bit
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636 |
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637 | ;All bits sucessfully received!
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638 |
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639 | mov temp,command ;Place system bits in "system"
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640 |
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641 | rol temp
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642 |
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643 | rol system
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644 |
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645 | rol temp
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646 |
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647 | rol system
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648 |
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649 |
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650 |
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651 | andi command,0b01111111
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652 |
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653 | andi system,0x1F
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654 |
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655 | ret
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656 |
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657 |
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658 |
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659 | fault:
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660 |
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661 | ser command ;Both "command" and "system"
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662 |
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663 | ser system ;0xFF indicates failure
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664 |
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665 | ret
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666 |
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667 |
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668 |
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669 | .eseg
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670 |
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671 | .org 0
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672 |
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673 | table:
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674 |
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675 | .db $00,$04 ;KTV1, button 4 default settings
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