Arrays vergleichen

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.Numeric_std.ALL;

entity debouncer is

   Generic( width : natural :=8);

    Port ( Input : in  STD_LOGIC_VECTOR (width-1 downto 0);

           Output : out  STD_LOGIC_VECTOR (width-1 downto 0);

           CLK : in  STD_LOGIC);

end debouncer;

architecture Behavioral of debouncer is

  type RegTyp is array (3 downto 0) of std_logic_vector(width-1 downto 0);

  signal ShiftReg : RegTyp := (others=> (others => '0'));

  begin

   process(CLK) begin

    if rising_edge(CLK) then

      ShiftReg <= ShiftReg(2 downto 0) & Input;

      if (ShiftReg(3)=ShifReg(2)) and (ShiftReg(2)=ShiftReg(1)) and (ShiftReg(1)=Shiftreg(0)) then

        Output<=Shiftreg(0);

      end if;

    end if;

   end process;

  end Behavioral;