1 | ----------------------------------------------------------------------------------
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2 | -- Company:
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3 | -- Engineer:
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4 | --
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5 | -- Create Date: 17:15:57 12/21/2009
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6 | -- Design Name:
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7 | -- Module Name: FLASH_CONTROLLER - Behavioral
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8 | -- Project Name:
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9 | -- Target Devices:
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10 | -- Tool versions:
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11 | -- Description:
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12 | --
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13 | -- Dependencies:
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14 | --
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15 | -- Revision:
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16 | -- Revision 0.01 - File Created
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17 | -- Additional Comments:
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18 | --
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19 | ----------------------------------------------------------------------------------
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20 | library IEEE;
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21 | use IEEE.STD_LOGIC_1164.ALL;
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22 | use IEEE.STD_LOGIC_ARITH.ALL;
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23 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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24 |
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25 | ---- Uncomment the following library declaration if instantiating
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26 | ---- any Xilinx primitives in this code.
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27 | --library UNISIM;
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28 | --use UNISIM.VComponents.all;
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29 |
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30 | entity FLASH_CONTROLLER is
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31 | Port (
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32 | ----------------------- NUR FÜR SIMULATION----------------------------------
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33 | ----------------------- KANN ENTFERNT WERDEN--------------------------------
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34 | DA_H : out std_logic_vector(7 downto 0);
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35 | DA_L : out std_logic_vector(7 downto 0);
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36 | DATA_EN_H : out std_logic;
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37 | DATA_EN_L : out std_logic;
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38 | BYTE_SR : out std_logic;
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39 | ADD_ZE : out std_logic;
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40 | ADD_V : out std_logic;
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41 | ADD_EN : out std_logic;
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42 |
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43 | BRAM_WR_RD_ENABLE : out std_logic;
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44 | BRAM_R_ADD_COUNT_ENABLE :out std_logic;
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45 | BRAM_R_ADD_COUNT_VOLL : out std_logic;
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46 | BRAM_R_ADD : out std_logic_VECTOR(13 downto 0):="11111111111111";
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47 | BRAM_R_ADD_ZERO : out std_logic;
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48 |
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49 | BRAM_CLK_1 : out std_logic;
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50 | BRAM_A_1 : out std_logic_VECTOR(13 downto 0);
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51 | BRAM_IN_DA_1 : out std_logic_vector (11 downto 0);
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52 | BRAM_OUT_DA_1 :out std_logic_vector (11 downto 0);
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53 | BRAM_WR_ENABLE_1 : out std_logic_vector (0 downto 0);
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54 |
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55 | BRAM_CLK_2 : out std_logic;
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56 | BRAM_A_2 :out std_logic_VECTOR(13 downto 0);
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57 | BRAM_IN_DA_2 :out std_logic_vector (11 downto 0);
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58 | BRAM_OUT_DA_2 : out std_logic_vector (11 downto 0);
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59 | BRAM_WR_ENABLE_2 :out std_logic_vector (0 downto 0);
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60 |
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61 | DA_FROM_FLASH : out std_logic_vector (11 downto 0);
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62 |
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63 |
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64 |
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65 |
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66 |
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67 | ----------------------------------------------------------------------------
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68 |
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69 | -------------------------STUER-UND DATENSIGNALE----------------------------
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70 |
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71 | BRAM_ADD_EN : out std_logic;
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72 | BRAM_WEAEN : out std_logic_vector(0 downto 0);
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73 | BADD : out std_logic_VECTOR(13 downto 0):="00000000000000";
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74 |
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75 | --READ_BRAM_CLK : in std_logic;
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76 | FLASH_ENABLE : in std_logic; -- ENABLE SIGNAL FÜR ZUSTANDSAUTOMATEN,WANN DARF DER AUTOMAT LOSLAUFEN WANN SOLL ER SCHLAFEN
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77 | FLASH_RESET : in STD_LOGIC; -- FLASH RESET VON MASTER RESET
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78 | FLASH_CLK : in STD_LOGIC; -- 40 MHZ TAKT 25 ns
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79 | FLASH_ADD : out std_logic_vector (23 downto 0); -- FLASH ADDRESSEN
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80 | FLASH_RP : out std_logic; -- CHIP RESET,DIENT ZUR BESCHÜTZUNG DER DATEN WENN GESCHRIEBEN WIRD(DA ABER NUR GELSEN WIRD KANN AUF 1 GESETZT WERDEN)
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81 | FLASH_CE : out std_logic; -- CHIP ENABLE
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82 | FLASH_OE : out std_logic; -- OUT ENABLE
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83 | FLASH_DATA : in STD_LOGIC_vector (7 downto 0); -- DATEN DIE IM FLASH EINGEBRANNT WURDEN (MIT IMPACT)
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84 | AUSGABE_DATEN_BRAM : out std_logic_vector (11 downto 0);
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85 | DATAOUT : out std_logic_vector (11 downto 0)); -- EINGEBRANNTE DATEN WERDEN HIER AUSGELESEN(DA 12 BIT BREITE DATEN;WIRD 2 BYTE ZUSSAMENGGESCHRIEBEN)
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86 |
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87 | ----------------------------------------------------------------------------
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88 | end FLASH_CONTROLLER;
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89 |
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90 | architecture Behavioral of FLASH_CONTROLLER is
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91 |
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92 | COMPONENT SINGLE_RAM_1
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93 | port (
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94 | clka: IN std_logic;
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95 | rsta: IN std_logic;
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96 | wea: IN std_logic_VECTOR(0 downto 0);
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97 | addra: IN std_logic_VECTOR(13 downto 0);
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98 | dina: IN std_logic_VECTOR(11 downto 0);
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99 | douta: OUT std_logic_VECTOR(11 downto 0));
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100 | End component;
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101 |
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102 | COMPONENT SINGLE_RAM_2
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103 | port (
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104 | clka: IN std_logic;
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105 | rsta: IN std_logic;
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106 | wea: IN std_logic_VECTOR(0 downto 0);
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107 | addra: IN std_logic_VECTOR(13 downto 0);
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108 | dina: IN std_logic_VECTOR(11 downto 0);
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109 | douta: OUT std_logic_VECTOR(11 downto 0));
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110 | End component;
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111 | ---------------------------------------------
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112 | -- HIFSSIGNAL FÜR FLASH AUSLESEN
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113 | Signal A : std_logic;
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114 | Signal CE,OE,RP : std_logic;
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115 | Signal ADD : std_logic_vector(23 downto 0):="000000000000000000000000";
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116 | Signal DATA_ENABLE_HI,DATA_ENABLE_LOW : std_logic;
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117 | Signal DA_HI : std_logic_vector(7 downto 0);
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118 | Signal DA_LOW : std_logic_vector (7 downto 0);
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119 | Signal BYTE_SCHREIBEN : std_logic;
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120 | Signal ADD_COUNT_ENABLE,ADD_VOLL,ADD_ZERO : std_logic;
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121 | -----------------------------------------------------------------------------------------
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122 | -- HILFSSIGNAL FÜR SCHREIBEN AUF BRAM
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123 | Signal BRAM_WRITE_ADD_COUNT_ENABLE : std_logic;
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124 | Signal BRAM_WRTIE_ADD : std_logic_VECTOR(13 downto 0):="11111111111111";
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125 | Signal BRAM_WRITE_ENABLE : std_logic;
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126 | Signal BRAM_WEA : std_logic_vector(0 downto 0);
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127 | Signal BRAM_WRITE_OR_READ_ENABLE : std_logic:='0';
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128 | Signal WRITE_OR_READ_COUNTER : integer range 0 to 2:=0;
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129 |
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130 |
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131 | -- HILFSSIGNAL FÜR LESEN DER BRAM
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132 |
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133 |
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134 | Signal BRAM_READ_ADD_COUNT_ENABLE : std_logic;
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135 | Signal BRAM_READ_ADD_COUNT_VOLL : std_logic:='0';
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136 | Signal BRAM_READ_ADD : std_logic_VECTOR(13 downto 0):="00000000000000";
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137 | Signal BRAM_READ_ADD_ZERO : std_logic;
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138 |
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139 | Signal BRAM_CLOCK_1 : std_logic;
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140 | Signal BRAM_ADD_1 : std_logic_VECTOR(13 downto 0);
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141 | Signal BRAM_IN_DATA_1 : std_logic_vector (11 downto 0);
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142 | Signal BRAM_OUT_DATA_1 : std_logic_vector (11 downto 0);
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143 | Signal BRAM_WRITE_ENABLE_1 : std_logic_vector (0 downto 0);
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144 |
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145 | Signal BRAM_CLOCK_2 : std_logic;
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146 | Signal BRAM_ADD_2 : std_logic_VECTOR(13 downto 0);
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147 | Signal BRAM_IN_DATA_2 : std_logic_vector (11 downto 0);
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148 | Signal BRAM_OUT_DATA_2 : std_logic_vector (11 downto 0);
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149 | Signal BRAM_WRITE_ENABLE_2 : std_logic_vector (0 downto 0);
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150 |
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151 | Signal DATA_FROM_FLASH : std_logic_vector (11 downto 0);
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152 |
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153 | -----------------------------------------------------------------------------------------------
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154 |
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155 | -------------------------------- ZUSTANDSAUTOMAT_FLASH_BRAM_SCHRREIBEN ----------------------------------------------
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156 | type STATE_TYPE_WRITE is (Grundzustand,Add_Zahlen,Warten_01,Warten_02,Warten_03,Warten_0,Warten_1,Warten_2,Lesen_0,Anlegen_1,Lesen_1,Anlegen_2,Lesen_2,Anlegen_3,Lesen_3,Anlegen_4,Lesen_4,Anlegen_5,Lesen_5,Anlegen_6,Lesen_6,Anlegen_7,Lesen_7,Schlafen);
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157 | Signal naechster_zustand: STATE_TYPE_WRITE;
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158 | Signal aktueller_zustand: STATE_TYPE_WRITE:=Schlafen;
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159 |
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160 | -----------------------------------------------------------------------------------------------
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161 |
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162 | -------------------------------- ZUSTANDSAUTOMAT_BRAM_LESEN ----------------------------------------------
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163 | type STATE_TYPE_READ is (Sleep,BRAM_1_AUSLESEN,WARTEN_LESEN_1,ADD_ANLEGEN_LESEN,WARTEN_AUF_SCHREIBEN);
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164 | Signal naechster_zustand_lesen: STATE_TYPE_READ;
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165 | Signal aktueller_zustand_lesen: STATE_TYPE_READ:=Sleep;
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166 |
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167 | -----------------------------------------------------------------------------------------------
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168 |
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169 | begin
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170 |
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171 |
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172 | DATAOUT <= DATA_FROM_FLASH;
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173 |
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174 |
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175 | FLASH_LESEN_BRAM_SCHRIEBEN_ZUSTAND_WEITERGEBEN:process (FLASH_CLK,FLASH_RESET)
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176 | begin
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177 | if FLASH_RESET = '1' then
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178 | aktueller_zustand<=Schlafen;--Grundzustand;
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179 | elsif rising_edge(Flash_CLK) then
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180 | aktueller_zustand <= naechster_zustand;
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181 | end if;
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182 | end process FLASH_LESEN_BRAM_SCHRIEBEN_ZUSTAND_WEITERGEBEN;
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183 | ---------------------------------------------
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184 |
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185 | Zustandsautomat_Write:process (aktueller_zustand,ADD_VOLL,FLASH_ENABLE)
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186 | begin
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187 | case aktueller_zustand is
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188 | -----------------------------------------------------------
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189 | when Schlafen => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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190 | BRAM_WRITE_ENABLE <= '0';
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191 |
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192 | ADD_COUNT_ENABLE <= '0'; -- DIESER ZUSTAND LÄßT DEN SPEICHER NICHT AUSLESEN
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193 | ADD_ZERO <= '0'; -- BIS DAS ENABLE SINGAL VOM EINGANG KOMMT, DANN
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194 | BYTE_SCHREIBEN <= '0'; -- STARTET DER AUTOMAT LOS DEN FLASH SPEICHER AUSZU-
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195 | DATA_ENABLE_HI <= '0'; -- LESEN
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196 | DATA_ENABLE_LOW <= '0'; --
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197 | CE <= '0'; --
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198 | OE <= '0'; --
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199 | RP <= '0'; --
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200 | if FLASH_ENABLE = '0' then --
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201 | naechster_zustand <= Schlafen; --
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202 | else --
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203 | naechster_zustand <=Grundzustand;--
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204 | end if; --
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205 | -----------------------------------------------------------
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206 | when Grundzustand =>
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207 | ADD_COUNT_ENABLE <= '0'; -- HIER STARTET DER ZUSTANDSAUTOMAT WENN ER ZUM ERSTEN MAL
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208 | ADD_ZERO <= '1'; -- GESTARTET WIRD ODER WENN DIE FLASH ADDRESSE VOLL GELAUFEN
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209 | BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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210 | BRAM_WRITE_ENABLE <= '0';
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211 |
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212 | if ADD_VOLL='1' then -- IST. HIER WIRD DIE FALSH ADDRESSE WIEDER AUF NULL ZURÜCK-
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213 | BYTE_SCHREIBEN <= '1'; -- GESETZT ODER FÄNGT MIT DER NULL AN.
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214 | else -- AUßERDEM WIRD HIER DURCH BYTE SCHREIBEN DATEN AUSGE-
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215 | BYTE_SCHREIBEN <= '0'; -- GEBEN WENN
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216 | end if; --
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217 | DATA_ENABLE_HI <= '0'; --
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218 | DATA_ENABLE_LOW <= '0'; --
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219 | CE <= '1'; --
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220 | OE <= '1'; --
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221 | RP <= '1'; --
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222 | naechster_zustand <= Warten_0; --
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223 | ----------------------------------------------------------- --
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224 |
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225 | -----------------------------------------------------------
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226 |
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227 | when Warten_0 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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228 | BRAM_WRITE_ENABLE <= '0';
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229 | if ADD_VOLL='1' then
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230 | BRAM_WRITE_ADD_COUNT_ENABLE <='1';
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231 | else
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232 | BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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233 | end if;
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234 | ADD_COUNT_ENABLE <= '0';
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235 | ADD_ZERO <= '0';
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236 | BYTE_SCHREIBEN <= '0';
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237 | DATA_ENABLE_HI <= '0';
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238 | DATA_ENABLE_LOW <= '0';
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239 | CE <= '0';
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240 | OE <= '0';
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241 | RP <= '1';
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242 | naechster_zustand <= Warten_1;
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243 |
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244 | when Warten_1 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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245 | BRAM_WRITE_ENABLE <= '0';
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246 |
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247 | ADD_COUNT_ENABLE <= '0';
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248 | ADD_ZERO <= '1';
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249 | BYTE_SCHREIBEN <= '0';
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250 | DATA_ENABLE_HI <= '0';
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251 | DATA_ENABLE_LOW <= '0';
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252 | CE <= '0';
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253 | OE <= '0';
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254 | RP <= '1';
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255 | naechster_zustand <= Warten_2;
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256 |
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257 | when Warten_2 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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258 | BRAM_WRITE_ENABLE <= '0';
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259 |
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260 | ADD_COUNT_ENABLE <= '0';
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261 | ADD_ZERO <= '0';
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262 | BYTE_SCHREIBEN <= '0';
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263 | DATA_ENABLE_HI <= '0';
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264 | DATA_ENABLE_LOW <= '0';
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265 | CE <= '0';
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266 | OE <= '0';
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267 | RP <= '1';
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268 | naechster_zustand <= Lesen_0;
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269 |
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270 | -------------------------------------------------------------
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271 | -------------------------------------------------------------
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272 | when Add_Zahlen => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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273 | BRAM_WRITE_ENABLE <= '0';
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274 |
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275 | ADD_COUNT_ENABLE <= '1'; -- DIESER ZUSTAND ZÄHLT DIE ADDRESSE WEITER DA DIE FLASH
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276 | ADD_ZERO <= '0'; -- ADDRESSE NOCH NICHT VOLLGELAUFEN IST. BENÖTIGT WIRD
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277 | BYTE_SCHREIBEN <= '1'; -- DIESER ZUSTAND UM DEN CACHE SPEICHER VOM FALSH NEU ZU
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278 | DATA_ENABLE_HI <= '0'; -- LADEN
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279 | DATA_ENABLE_LOW <= '0'; --
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280 | CE <= '1'; --
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281 | OE <= '1'; --
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282 | RP <= '1'; --
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283 | naechster_zustand <= Warten_01; --
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284 |
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285 |
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286 |
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287 | when Warten_01 => BRAM_WRITE_ADD_COUNT_ENABLE <='1';
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288 | BRAM_WRITE_ENABLE <= '0';
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289 | --BRAM_TAKT_20MHZ <= '0';
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290 | ADD_COUNT_ENABLE <= '0';
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291 | ADD_ZERO <= '0';
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292 | BYTE_SCHREIBEN <= '0';
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293 | DATA_ENABLE_HI <= '0';
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294 | DATA_ENABLE_LOW <= '0';
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295 | CE <= '0';
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296 | OE <= '0';
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297 | RP <= '1';
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298 | naechster_zustand <= Warten_02;
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299 |
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300 | when Warten_02 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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301 | BRAM_WRITE_ENABLE <= '1';
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302 | --BRAM_TAKT_20MHZ <= '0';
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303 | ADD_COUNT_ENABLE <= '0';
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304 | ADD_ZERO <= '0';
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305 | BYTE_SCHREIBEN <= '0';
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306 | DATA_ENABLE_HI <= '0';
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307 | DATA_ENABLE_LOW <= '0';
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308 | CE <= '0';
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309 | OE <= '0';
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310 | RP <= '1';
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311 | naechster_zustand <= Warten_03;
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312 |
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313 | when Warten_03 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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314 | BRAM_WRITE_ENABLE <= '0';
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315 | --BRAM_TAKT_20MHZ <= '0';
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316 | ADD_COUNT_ENABLE <= '0';
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317 | ADD_ZERO <= '0';
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318 | BYTE_SCHREIBEN <= '0';
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319 | DATA_ENABLE_HI <= '0';
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320 | DATA_ENABLE_LOW <= '0';
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321 | CE <= '0';
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322 | OE <= '0';
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323 | RP <= '1';
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324 | naechster_zustand <= Lesen_0;
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325 | ------------------------------------------------------------
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326 |
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327 |
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328 |
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329 |
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330 |
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331 | when Lesen_0 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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332 | BRAM_WRITE_ENABLE <= '0';
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333 |
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334 |
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335 | ADD_COUNT_ENABLE <= '0';
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336 | ADD_ZERO <= '0';
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337 | BYTE_SCHREIBEN <= '0';
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338 | DATA_ENABLE_HI <= '1';
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339 | DATA_ENABLE_LOW <= '0';
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340 | CE <= '0';
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341 | OE <= '0';
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342 | RP <= '1';
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343 | if ADD_VOLL = '1' then
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344 | naechster_zustand <= Grundzustand;
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345 | else
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346 | naechster_zustand <= Anlegen_1;
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347 | end if;
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348 |
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349 |
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350 | when Anlegen_1 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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351 | BRAM_WRITE_ENABLE <= '0';
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352 |
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353 | ADD_COUNT_ENABLE <= '1';
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354 | ADD_ZERO <= '0';
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355 | BYTE_SCHREIBEN <= '0';
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356 | DATA_ENABLE_HI <= '0';
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357 | DATA_ENABLE_LOW <= '0';
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358 | CE <= '0';
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359 | OE <= '0';
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360 | RP <= '1';
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361 | naechster_zustand <= Lesen_1;
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362 |
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363 |
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364 | when Lesen_1 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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365 | BRAM_WRITE_ENABLE <= '0';
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366 |
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367 |
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368 | ADD_COUNT_ENABLE <= '0';
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369 | ADD_ZERO <= '0';
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370 | BYTE_SCHREIBEN <= '0';
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371 | DATA_ENABLE_HI <= '0';
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372 | DATA_ENABLE_LOW <= '1';
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373 | CE <= '0';
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374 | OE <= '0';
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375 | RP <= '1';
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376 | if ADD_VOLL = '1' then
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377 | naechster_zustand <= Grundzustand;
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378 | else
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379 | naechster_zustand <= Anlegen_2;
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380 | end if;
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381 |
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382 | when Anlegen_2 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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383 | BRAM_WRITE_ENABLE <= '0';
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384 | --BRAM_TAKT_20MHZ <= '1';
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385 | ADD_COUNT_ENABLE <= '1';
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386 | ADD_ZERO <= '0';
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387 | BYTE_SCHREIBEN <= '1';
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388 | DATA_ENABLE_HI <= '0';
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389 | DATA_ENABLE_LOW <= '0';
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390 | CE <= '0';
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391 | OE <= '0';
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392 | RP <= '1';
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393 | naechster_zustand <= Lesen_2;
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394 |
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395 | when Lesen_2 => BRAM_WRITE_ADD_COUNT_ENABLE <='1';
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396 | BRAM_WRITE_ENABLE <= '0';
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397 |
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398 | ADD_COUNT_ENABLE <= '0';
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399 | ADD_ZERO <= '0';
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400 | BYTE_SCHREIBEN <= '0';
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401 | DATA_ENABLE_HI <= '1';
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402 | DATA_ENABLE_LOW <= '0';
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403 | CE <= '0';
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404 | OE <= '0';
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405 | RP <= '1';
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406 | if ADD_VOLL = '1' then
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407 | naechster_zustand <= Grundzustand;
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408 | else
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409 | naechster_zustand <= Anlegen_3;
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410 | end if;
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411 |
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412 |
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413 | when Anlegen_3 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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414 | BRAM_WRITE_ENABLE <= '1';
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415 |
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416 | ADD_COUNT_ENABLE <= '1';
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417 | ADD_ZERO <= '0';
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418 | BYTE_SCHREIBEN <= '0';
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419 | DATA_ENABLE_HI <= '0';
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420 | DATA_ENABLE_LOW <= '0';
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421 | CE <= '0';
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422 | OE <= '0';
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423 | RP <= '1';
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424 | naechster_zustand <= Lesen_3;
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425 |
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426 |
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427 | when Lesen_3 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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428 | BRAM_WRITE_ENABLE <= '0';
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429 |
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430 | ADD_COUNT_ENABLE <= '0';
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431 | ADD_ZERO <= '0';
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432 | BYTE_SCHREIBEN <= '0';
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433 | DATA_ENABLE_HI <= '0';
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434 | DATA_ENABLE_LOW <= '1';
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435 | CE <= '0';
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436 | OE <= '0';
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437 | RP <= '1';
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438 | if ADD_VOLL = '1' then
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439 | naechster_zustand <= Grundzustand;
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440 | else
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441 | naechster_zustand <= Anlegen_4;
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442 | end if;
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443 |
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444 | when Anlegen_4 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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445 | BRAM_WRITE_ENABLE <= '0';
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446 |
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447 |
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448 | ADD_COUNT_ENABLE <= '1';
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449 | ADD_ZERO <= '0';
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450 | BYTE_SCHREIBEN <= '1';
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451 | DATA_ENABLE_HI <= '0';
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452 | DATA_ENABLE_LOW <= '0';
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453 | CE <= '0';
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454 | OE <= '0';
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455 | RP <= '1';
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456 | naechster_zustand <= Lesen_4;
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457 |
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458 | when Lesen_4 => BRAM_WRITE_ADD_COUNT_ENABLE <='1';
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459 | BRAM_WRITE_ENABLE <= '0';
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460 |
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461 |
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462 | ADD_COUNT_ENABLE <= '0';
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463 | ADD_ZERO <= '0';
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464 | BYTE_SCHREIBEN <= '0';
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465 | DATA_ENABLE_HI <= '1';
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466 | DATA_ENABLE_LOW <= '0';
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467 | CE <= '0';
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468 | OE <= '0';
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469 | RP <= '1';
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470 | if ADD_VOLL = '1' then
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471 | naechster_zustand <= Grundzustand;
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472 | else
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473 | naechster_zustand <= Anlegen_5;
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474 | end if;
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475 |
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476 |
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477 | when Anlegen_5 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
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478 | BRAM_WRITE_ENABLE <= '1';
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479 |
|
480 | ADD_COUNT_ENABLE <= '1';
|
481 | ADD_ZERO <= '0';
|
482 | BYTE_SCHREIBEN <= '0';
|
483 | DATA_ENABLE_HI <= '0';
|
484 | DATA_ENABLE_LOW <= '0';
|
485 | CE <= '0';
|
486 | OE <= '0';
|
487 | RP <= '1';
|
488 | naechster_zustand <= Lesen_5;
|
489 |
|
490 |
|
491 | when Lesen_5 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
|
492 | BRAM_WRITE_ENABLE <= '0';
|
493 |
|
494 | ADD_COUNT_ENABLE <= '0';
|
495 | ADD_ZERO <= '0';
|
496 | BYTE_SCHREIBEN <= '0';
|
497 | DATA_ENABLE_HI <= '0';
|
498 | DATA_ENABLE_LOW <= '1';
|
499 | CE <= '0';
|
500 | OE <= '0';
|
501 | RP <= '1';
|
502 | if ADD_VOLL = '1' then
|
503 | naechster_zustand <= Grundzustand;
|
504 | else
|
505 | naechster_zustand <= Anlegen_6;
|
506 | end if;
|
507 |
|
508 | when Anlegen_6 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
|
509 | BRAM_WRITE_ENABLE <= '0';
|
510 |
|
511 | ADD_COUNT_ENABLE <= '1';
|
512 | ADD_ZERO <= '0';
|
513 | BYTE_SCHREIBEN <= '1';
|
514 | DATA_ENABLE_HI <= '0';
|
515 | DATA_ENABLE_LOW <= '0';
|
516 | CE <= '0';
|
517 | OE <= '0';
|
518 | RP <= '1';
|
519 | naechster_zustand <= Lesen_6;
|
520 |
|
521 | when Lesen_6 => BRAM_WRITE_ADD_COUNT_ENABLE <='1';
|
522 | BRAM_WRITE_ENABLE <= '0';
|
523 |
|
524 | ADD_COUNT_ENABLE <= '0';
|
525 | ADD_ZERO <= '0';
|
526 | BYTE_SCHREIBEN <= '0';
|
527 | DATA_ENABLE_HI <= '1';
|
528 | DATA_ENABLE_LOW <= '0';
|
529 | CE <= '0';
|
530 | OE <= '0';
|
531 | RP <= '1';
|
532 | if ADD_VOLL = '1' then
|
533 | naechster_zustand <= Grundzustand;
|
534 | else
|
535 | naechster_zustand <= Anlegen_7;
|
536 | end if;
|
537 |
|
538 |
|
539 | when Anlegen_7 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
|
540 | BRAM_WRITE_ENABLE <= '1';
|
541 |
|
542 | ADD_COUNT_ENABLE <= '1';
|
543 | ADD_ZERO <= '0';
|
544 | BYTE_SCHREIBEN <= '0';
|
545 | DATA_ENABLE_HI <= '0';
|
546 | DATA_ENABLE_LOW <= '0';
|
547 | CE <= '0';
|
548 | OE <= '0';
|
549 | RP <= '1';
|
550 | naechster_zustand <= Lesen_7;
|
551 |
|
552 |
|
553 | when Lesen_7 => BRAM_WRITE_ADD_COUNT_ENABLE <='0';
|
554 | BRAM_WRITE_ENABLE <= '0';
|
555 |
|
556 | ADD_COUNT_ENABLE <= '0';
|
557 | ADD_ZERO <= '0';
|
558 | BYTE_SCHREIBEN <= '0';
|
559 | DATA_ENABLE_HI <= '0';
|
560 | DATA_ENABLE_LOW <= '1';
|
561 | CE <= '0';
|
562 | OE <= '0';
|
563 | RP <= '1';
|
564 | if FLASH_ENABLE = '1' then
|
565 | if ADD_VOLL = '1' then
|
566 | naechster_zustand <= Grundzustand;
|
567 | else
|
568 | naechster_zustand <= Add_Zahlen;
|
569 | end if;
|
570 | else
|
571 | naechster_zustand <= schlafen;
|
572 | end if;
|
573 |
|
574 | end case;
|
575 | end process Zustandsautomat_Write;
|
576 | -------------------------------------------------
|
577 | FLASH_ADDRESSEN_AUSLESEN: process (FLASH_CLK)
|
578 | begin
|
579 |
|
580 | if falling_edge(FLASH_CLK) then
|
581 | if ADD_COUNT_ENABLE = '1' then
|
582 | ADD<=ADD+1;
|
583 | elsif ADD_ZERO = '1' then
|
584 | ADD <= "000000000000000000000000";
|
585 | else
|
586 | ADD <= ADD;
|
587 | end if;
|
588 | end if;
|
589 | end process FLASH_ADDRESSEN_AUSLESEN;
|
590 | -------------------------------------------------
|
591 | TEST: process (FLASH_CLK)
|
592 | begin
|
593 | if rising_edge(FLASH_CLK) then
|
594 | if ADD = "000000000100000110011101" then
|
595 | ADD_VOLL<='1';
|
596 | else
|
597 | ADD_VOLL<='0';
|
598 | end if;
|
599 | end if;
|
600 | end process TEST;
|
601 | -------------------------------------------------
|
602 | FLASH_DATEN_EINLESEN_HI_BITS: process (FLASH_CLK)
|
603 | begin
|
604 | if falling_edge(FLASH_CLK) then
|
605 | if DATA_ENABLE_HI = '1' then
|
606 | DA_HI<=FLASH_DATA;
|
607 | else
|
608 | DA_HI<=DA_HI;
|
609 | end if;
|
610 | end if;
|
611 | end process FLASH_DATEN_EINLESEN_HI_BITS;
|
612 | -------------------------------------------------
|
613 | FLASH_DATEN_EINLESEN_LOW_BITS: process (FLASH_CLK)
|
614 | begin
|
615 | if falling_edge(FLASH_CLK) then
|
616 | if DATA_ENABLE_LOW = '1' then
|
617 | DA_LOW<=FLASH_DATA;
|
618 | else
|
619 | DA_LOW<=DA_LOW;
|
620 | end if;
|
621 | end if;
|
622 | end process FLASH_DATEN_EINLESEN_LOW_BITS;
|
623 | -------------------------------------------------
|
624 | BYTE_ZUSAMENSETZEN: process (FLASH_CLK)
|
625 | begin
|
626 | if falling_edge (FLASH_CLK) then
|
627 | if BYTE_SCHREIBEN = '1' then
|
628 | DATA_FROM_FLASH <= DA_HI(3 downto 0) & DA_LOW;
|
629 | end if;
|
630 |
|
631 | end if;
|
632 | end process BYTE_ZUSAMENSETZEN;
|
633 |
|
634 | -----------------------------------------------------
|
635 |
|
636 |
|
637 | -- BRAM ADD COUNTER UND WRITE ENABLE -----------------------
|
638 |
|
639 | BRAM_WRITE_ADD_ZAHLEN:process (FLASH_CLK)
|
640 | begin
|
641 | if falling_edge (FLASH_CLK) then
|
642 | if BRAM_WRITE_ADD_COUNT_ENABLE = '1' then
|
643 | BRAM_WRTIE_ADD <=BRAM_WRTIE_ADD+1;
|
644 | elsif ADD_ZERO = '1' then
|
645 | BRAM_WRTIE_ADD <= "11111111111111";
|
646 | else
|
647 | BRAM_WRTIE_ADD <=BRAM_WRTIE_ADD;
|
648 | end if;
|
649 | end if;
|
650 | end process BRAM_WRITE_ADD_ZAHLEN;
|
651 |
|
652 | BRAM_WRITE_ENABLE_ANLEGEN:process (FLASH_CLK)
|
653 | begin
|
654 | if falling_edge (FLASH_CLK) then
|
655 | if BRAM_WRITE_ENABLE = '1' then
|
656 | BRAM_WEA <="1";
|
657 | else
|
658 | BRAM_WEA <="0";
|
659 | end if;
|
660 | end if;
|
661 | end process BRAM_WRITE_ENABLE_ANLEGEN;
|
662 |
|
663 |
|
664 |
|
665 |
|
666 |
|
667 | ----------------------------------------------------------------------
|
668 |
|
669 | ----------------------------------------------------------------------
|
670 | ----------------------------------------------------------------------
|
671 | FLASHDATEN_INS_RAM_UEBERNEHMEN_COUNTER: process (ADD_VOLL)
|
672 | begin
|
673 | if ADD_VOLL ='1' then
|
674 | WRITE_OR_READ_COUNTER <= WRITE_OR_READ_COUNTER + 1;
|
675 | elsif WRITE_OR_READ_COUNTER > 1 then
|
676 | WRITE_OR_READ_COUNTER <= 0;
|
677 | else
|
678 | WRITE_OR_READ_COUNTER <= 1;
|
679 | end if;
|
680 | end process FLASHDATEN_INS_RAM_UEBERNEHMEN_COUNTER;
|
681 |
|
682 |
|
683 | BRAM_WRITE_OR_READ_ENABLE <= '1' when WRITE_OR_READ_COUNTER = 1 else-- überflüssig, ist gleich sezten
|
684 | '0' when WRITE_OR_READ_COUNTER = 0 else
|
685 | '1';
|
686 | -----------------------------------------------------------------------
|
687 |
|
688 |
|
689 |
|
690 |
|
691 | ----------------------------- UMSCHLATER FÜR BRAM's------------------------------------
|
692 | ---------------------------------------------------------------------------------------------------------------
|
693 | BRAM_CLOCK_1 <= FLASH_CLK;
|
694 |
|
695 | BRAM_ADD_1 <= BRAM_WRTIE_ADD when BRAM_WRITE_OR_READ_ENABLE = '1' else
|
696 | BRAM_READ_ADD when BRAM_WRITE_OR_READ_ENABLE = '0' ;
|
697 |
|
698 | BRAM_WRITE_ENABLE_1 <= BRAM_WEA when BRAM_WRITE_OR_READ_ENABLE = '1' else
|
699 | "0" when BRAM_WRITE_OR_READ_ENABLE = '0' else
|
700 | "0";
|
701 |
|
702 | BRAM_IN_DATA_1 <= DATA_FROM_FLASH;
|
703 | ---------------------------------------------------------------------------------
|
704 | BRAM_CLOCK_2 <= FLASH_CLK;
|
705 |
|
706 |
|
707 | BRAM_ADD_2 <= BRAM_READ_ADD when BRAM_WRITE_OR_READ_ENABLE = '1' else
|
708 | BRAM_WRTIE_ADD when BRAM_WRITE_OR_READ_ENABLE = '0' ;
|
709 |
|
710 | BRAM_WRITE_ENABLE_2 <= "0" when BRAM_WRITE_OR_READ_ENABLE = '1' else
|
711 | BRAM_WEA when BRAM_WRITE_OR_READ_ENABLE = '0' else
|
712 | "0";
|
713 |
|
714 | BRAM_IN_DATA_2 <= DATA_FROM_FLASH;
|
715 |
|
716 | -----------------------------------------------------------------------------------
|
717 |
|
718 | AUSGABE_DATEN_BRAM <= BRAM_OUT_DATA_1 when BRAM_WRITE_OR_READ_ENABLE = '1' else
|
719 | BRAM_OUT_DATA_2 when BRAM_WRITE_OR_READ_ENABLE = '0';
|
720 | ---------------------------------------------------------------------------------
|
721 |
|
722 |
|
723 |
|
724 |
|
725 |
|
726 |
|
727 | ---------------------------------------------------------------------------------------------------------------
|
728 | ----------------------------------ZUSTANDSAUTOMAT FÜR BRAM LESEN-----------------------------------------------
|
729 | ---------------------------------------------------------------------------------------------------------------
|
730 | ---------------------------------------------------------------------------------------------------------------
|
731 |
|
732 | BRAM_LESEN_ZUSTAND_WEITERGEBEN:process (FLASH_CLK,FLASH_RESET)
|
733 | begin
|
734 | if FLASH_RESET = '1' then
|
735 | aktueller_zustand_lesen<=Sleep;
|
736 | elsif rising_edge(FLASH_CLK) then
|
737 | aktueller_zustand_lesen <= naechster_zustand_lesen;
|
738 |
|
739 | end if;
|
740 | end process BRAM_LESEN_ZUSTAND_WEITERGEBEN;
|
741 |
|
742 |
|
743 | Zustandsautomat_Read:process (aktueller_zustand_lesen,BRAM_READ_ADD_COUNT_VOLL,ADD_VOLL,FLASH_ENABLE)
|
744 | begin
|
745 | case aktueller_zustand_lesen is
|
746 | -----------------------------------------------------------
|
747 | when Sleep => BRAM_READ_ADD_COUNT_ENABLE <= '0';
|
748 | BRAM_READ_ADD_ZERO <= '1';
|
749 | if FLASH_ENABLE = '1' then
|
750 | naechster_zustand_lesen <= ADD_ANLEGEN_LESEN;
|
751 | else
|
752 | naechster_zustand_lesen <= Sleep;
|
753 | end if;
|
754 |
|
755 | when ADD_ANLEGEN_LESEN => BRAM_READ_ADD_COUNT_ENABLE <= '0';
|
756 | BRAM_READ_ADD_ZERO <= '1';
|
757 | naechster_zustand_lesen <= WARTEN_LESEN_1;
|
758 |
|
759 |
|
760 | when BRAM_1_AUSLESEN => BRAM_READ_ADD_COUNT_ENABLE <= '1';
|
761 | BRAM_READ_ADD_ZERO <= '0';
|
762 |
|
763 | if BRAM_READ_ADD_COUNT_VOLL = '1' then
|
764 | naechster_zustand_lesen <= WARTEN_AUF_SCHREIBEN;
|
765 | else
|
766 | naechster_zustand_lesen <=WARTEN_LESEN_1;
|
767 | end if;
|
768 |
|
769 | when WARTEN_LESEN_1 => BRAM_READ_ADD_COUNT_ENABLE <= '0';
|
770 | BRAM_READ_ADD_ZERO <= '0';
|
771 | naechster_zustand_lesen <= BRAM_1_AUSLESEN;
|
772 |
|
773 |
|
774 |
|
775 | when WARTEN_AUF_SCHREIBEN => BRAM_READ_ADD_COUNT_ENABLE <= '0';
|
776 | BRAM_READ_ADD_ZERO <= '0';
|
777 | if ADD_VOLL = '1' then
|
778 | naechster_zustand_lesen <= Sleep;
|
779 | else
|
780 | naechster_zustand_lesen <=WARTEN_AUF_SCHREIBEN;
|
781 | end if;
|
782 |
|
783 | end case;
|
784 | end process Zustandsautomat_Read;
|
785 |
|
786 |
|
787 | RAM_READ_ADD_ZAHLEN:process (FLASH_CLK)
|
788 | begin
|
789 | if falling_edge (FLASH_CLK) then
|
790 | if BRAM_READ_ADD_COUNT_ENABLE = '1' then
|
791 | BRAM_READ_ADD <= BRAM_READ_ADD+1;
|
792 | elsif BRAM_READ_ADD_ZERO = '1' then
|
793 | BRAM_READ_ADD <= "00000000000000";
|
794 | elsif ADD_VOLL ='1' then
|
795 | BRAM_READ_ADD <= "00000000000000";
|
796 | else
|
797 |
|
798 | BRAM_READ_ADD <= BRAM_READ_ADD;
|
799 | end if;
|
800 | end if;
|
801 | end process RAM_READ_ADD_ZAHLEN;
|
802 |
|
803 | RAM_READ_ADD_VOLL:process (FLASH_CLK)
|
804 | begin
|
805 | if rising_edge (FLASH_CLK) then
|
806 | if BRAM_READ_ADD > "10000011001101" then
|
807 | BRAM_READ_ADD_COUNT_VOLL <= '1';
|
808 | else
|
809 | BRAM_READ_ADD_COUNT_VOLL <= '0';
|
810 | end if;
|
811 | end if;
|
812 | end process RAM_READ_ADD_VOLL;
|
813 |
|
814 | -----------------------------------------------------------------------------------------------------------
|
815 | -----------------------------------------------------------------------------------------------------------
|
816 |
|
817 | --------------NUR FÜR SIMULATION---------------------
|
818 | -----------------------------------------------------
|
819 | DATA_EN_H <= DATA_ENABLE_HI;
|
820 | DATA_EN_L <= DATA_ENABLE_LOW;
|
821 | DA_H <= DA_HI;
|
822 | DA_L <= DA_LOW;
|
823 | BYTE_SR <= BYTE_SCHREIBEN;
|
824 | ADD_ZE <= ADD_ZERO;
|
825 | ADD_V <= ADD_VOLL;
|
826 | ADD_EN <= ADD_COUNT_ENABLE;
|
827 | BRAM_ADD_EN <= BRAM_WRITE_ADD_COUNT_ENABLE;
|
828 | BRAM_WEAEN <= BRAM_WEA;
|
829 | BADD <= BRAM_WRTIE_ADD;
|
830 |
|
831 | BRAM_WR_RD_ENABLE <= BRAM_WRITE_OR_READ_ENABLE;
|
832 |
|
833 |
|
834 | BRAM_R_ADD_COUNT_ENABLE <= BRAM_READ_ADD_COUNT_ENABLE;
|
835 | BRAM_R_ADD_COUNT_VOLL <= BRAM_READ_ADD_COUNT_VOLL ;
|
836 | BRAM_R_ADD <= BRAM_READ_ADD;
|
837 | BRAM_R_ADD_ZERO <= BRAM_READ_ADD_ZERO;
|
838 |
|
839 | BRAM_CLK_1 <= BRAM_CLOCK_1 ;
|
840 | BRAM_A_1 <= BRAM_ADD_1;
|
841 | BRAM_IN_DA_1 <= BRAM_IN_DATA_1;
|
842 | BRAM_OUT_DA_1 <= BRAM_OUT_DATA_1;
|
843 | BRAM_WR_ENABLE_1 <= BRAM_WRITE_ENABLE_1;
|
844 |
|
845 | BRAM_CLK_2 <= BRAM_CLOCK_2;
|
846 | BRAM_A_2 <= BRAM_ADD_2 ;
|
847 | BRAM_IN_DA_2 <= BRAM_IN_DATA_2;
|
848 | BRAM_OUT_DA_2 <= BRAM_OUT_DATA_2;
|
849 | BRAM_WR_ENABLE_2 <= BRAM_WRITE_ENABLE_2;
|
850 |
|
851 | DA_FROM_FLASH <= DATA_FROM_FLASH ;
|
852 |
|
853 | --------------------------------------------------------
|
854 |
|
855 | ------------------------------------------------------
|
856 | ---------------------HILFSSIGNALE---------------------
|
857 | --DATA_FROM_FLASH <= DATAOUT ;
|
858 | FLASH_RP <= RP;
|
859 | FLASH_CE <= CE;
|
860 | FLASH_OE <= OE;
|
861 | FLASH_ADD <=ADD;
|
862 |
|
863 | -------------------------------------------------
|
864 |
|
865 |
|
866 | --------------PORT MAPPING ----------------
|
867 |
|
868 | RAM_EINLESEN_1:SINGLE_RAM_1
|
869 |
|
870 | PORT MAP ( clka => BRAM_CLOCK_1,
|
871 | rsta => FLASH_RESET,
|
872 | addra => BRAM_ADD_1,
|
873 | wea => BRAM_WRITE_ENABLE_1,
|
874 | dina => BRAM_IN_DATA_1,
|
875 | douta => BRAM_OUT_DATA_1);
|
876 |
|
877 |
|
878 | RAM_EINLESEN_2:SINGLE_RAM_2
|
879 |
|
880 | PORT MAP ( clka => BRAM_CLOCK_2,
|
881 | rsta => FLASH_RESET,
|
882 | addra => BRAM_ADD_2,
|
883 | wea => BRAM_WRITE_ENABLE_2,
|
884 | dina => BRAM_IN_DATA_2,
|
885 | douta => BRAM_OUT_DATA_2);
|
886 | end Behavioral;
|