Global Clock implementieren klappt nicht

entity MAIN_STRUKTUR is

    Port ( MASTER_CLK                : in    std_logic; -- 27 MHZ EINGANG

           MASTER_EINGANG            : in   STD_LOGIC_VECTOR  (11 downto 0);

           MASTER_RESET               : in   STD_LOGIC;

           SYSTEM_CLK_200MHZ_P        : in   std_logic; 

           SYSTEM_CLK_200MHZ_N        : in    std_logic;

           CLK_200MHZ                 : out  std_logic;

end MAIN_STRUKTUR;

architecture Behavioral of MAIN_STRUKTUR is

begin

   -- IBUFGDS: Differential Global Clock Input Buffer

   --          Spartan-6

   -- Xilinx HDL Language Template, version 11.3

   IBUFGDS_inst : IBUFGDS

   generic map (

      DIFF_TERM => FALSE, -- Differential Termination 

      IOSTANDARD => "DEFAULT")

   port map (

      O =>   CLK_200MHZ,  -- Clock buffer output

      I =>  SYSTEM_CLK_200MHZ_P,  -- Diff_p clock buffer input (connect directly to top-level port)

      IB => SYSTEM_CLK_200MHZ_N -- Diff_n clock buffer input (connect directly to top-level port)

   );

   -- End of IBUFGDS_inst instantiation

END Behavioral;

ERROR:HDLCompiler:69 - "D:\VHDL TUTORIAL\SIMULATOR_PULS\MAIN_STRUKTUR.vhd" Line 136: <ibufgds> is not declared.

 Begin [/Begin] mache kommt ein Syntax Fehler:

[vhdl]

ERROR:HDLCompiler:806 - "D:\VHDL TUTORIAL\SIMULATOR_PULS\MAIN_STRUKTUR.vhd" Line 60: Syntax error near "IBUFGDS_inst".