1 | /**************************************************************************
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2 | * Includes
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3 | *************************************************************************/
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4 | #include "lpc2478.h" /* LPC23xx/24xx definitions */
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5 | #include "dma.h"
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6 | #include "irq.h"
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7 |
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8 | volatile U32 DMATCCount = 0;
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9 | volatile U32 DMAErrCount = 0;
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10 |
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11 | volatile U32 llist[37][4];
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12 |
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13 |
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14 | /**************************************************************************
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15 | ** Function name: DMAHandler
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16 | **
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17 | ** Descriptions: DMA interrupt handler
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18 | **
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19 | ** parameters: None
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20 | ** Returned value: None
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21 | **************************************************************************/
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22 | void DMAHandler (void) __irq
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23 | {
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24 | U32 regVal;
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25 |
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26 | regVal = GPDMA_INT_TCSTAT;
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27 | if ( regVal )
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28 | {
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29 | DMATCCount++;
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30 | GPDMA_INT_TCCLR |= regVal;
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31 | }
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32 |
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33 | regVal = GPDMA_INT_ERR_STAT;
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34 | if ( regVal )
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35 | {
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36 | DMAErrCount++;
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37 | GPDMA_INT_ERR_CLR |= regVal;
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38 | }
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39 |
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40 | VICVectAddr = 0; /* Acknowledge Interrupt */
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41 | }
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42 |
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43 | /**************************************************************************
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44 | ** Function name: DMA_Init
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45 | **
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46 | ** Descriptions:
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47 | **
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48 | ** parameters:
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49 | ** Returned value:
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50 | **************************************************************************/
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51 | U8 DMA_Init( U8 DMAMode )
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52 | {
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53 |
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54 | U8 i;
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55 | PCONP |= (1 << 29); /* Enable GPDMA clock */
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56 |
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57 | /* clear all interrupts on channel 0 */
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58 | GPDMA_INT_TCCLR = 0x01;
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59 | GPDMA_INT_ERR_CLR = 0x01;
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60 |
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61 | if ( DMAMode == M2M )
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62 | {
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63 | GPDMA_CH0_SRC = DMA_SRC;
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64 | GPDMA_CH0_DEST = DMA_DST;
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65 |
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66 | for (i = 0; i<=35;i++)
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67 | {
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68 | llist[i][0]=0xA0000000+(DMA_SIZE/4) + ((DMA_SIZE/4)*i); // SRC
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69 | llist[i][1]=0xA0025800+(DMA_SIZE/4) + ((DMA_SIZE/4)*i); // DST
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70 | llist[i][2]=(U32)llist[i+1]; // NEXT LL
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71 | llist[i][3]=0x0c4a4040; // COMAND
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72 | }
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73 |
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74 | llist[36][0] = 0xA0000000+(DMA_SIZE/4) + ((DMA_SIZE/4)*35);
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75 | llist[36][1] = 0xA0025800+(DMA_SIZE/4) + ((DMA_SIZE/4)*35);
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76 | llist[36][2] = 0;
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77 | llist[36][3] = 0x0c4a4040;
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78 |
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79 | /* Terminal Count Int enable */
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80 | GPDMA_CH0_CTRL = ((DMA_SIZE/4) & 0x0FFF) // Transver Size
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81 | | (0x04 << 12) // Source burst size
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82 | | (0x04 << 15) // Destination burst Size
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83 | | (0x02 << 18) // Source width
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84 | | (0x02 << 21) // destination width
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85 | | (1 << 26) // Source increment
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86 | | (1 << 27) // Destination increment
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87 | | 0x80000000;
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88 |
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89 | GPDMA_CH0_LLI = (U32)llist[0] & 0xFFFFFFFC;
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90 | }
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91 | else
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92 | {
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93 | return ( FALSE );
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94 | }
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95 |
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96 | GPDMA_CONFIG = 0x01; /* Enable DMA channels, little endian */
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97 |
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98 | while ( !(GPDMA_CONFIG & 0x01) );
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99 |
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100 | if ( install_irq( GPDMA_INT, (void *)DMAHandler, HIGHEST_PRIORITY ) == FALSE )
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101 | {
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102 | return ( FALSE );
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103 | }
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104 | return (TRUE);
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105 | }
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