1 | #include "msp430x54x.h"
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2 |
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3 | #define Num_of_Results 8
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4 |
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5 | volatile unsigned int A0results[Num_of_Results];
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6 | volatile unsigned int A1results[Num_of_Results];
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7 | volatile unsigned int A2results[Num_of_Results];
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8 | volatile unsigned int A3results[Num_of_Results];
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9 |
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10 | void main(void)
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11 | {
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12 | WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer
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13 | P6SEL = 0x0F; // Enable A/D channel inputs
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14 | ADC12CTL0 = ADC12ON+ADC12MSC+ADC12SHT0_8; // Turn on ADC12, extend sampling time
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15 | // to avoid overflow of results
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16 | ADC12CTL1 = ADC12SHP+ADC12CONSEQ_3; // Use sampling timer, repeated sequence
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17 | ADC12MCTL0 = ADC12INCH_0; // ref+=AVcc, channel = A0
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18 | ADC12MCTL1 = ADC12INCH_1; // ref+=AVcc, channel = A1
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19 | ADC12MCTL2 = ADC12INCH_2; // ref+=AVcc, channel = A2
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20 | ADC12MCTL3 = ADC12INCH_3+ADC12EOS; // ref+=AVcc, channel = A3, end seq.
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21 | ADC12IE = 0x08; // Enable ADC12IFG.3
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22 | ADC12CTL0 |= ADC12ENC; // Enable conversions
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23 | ADC12CTL0 |= ADC12SC; // Start convn - software trigger
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24 |
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25 | __bis_SR_register(LPM0_bits + GIE); // Enter LPM0, Enable interrupts
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26 | __no_operation(); // For debugger
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27 |
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28 | }
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29 |
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30 | #pragma vector=ADC12_VECTOR
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31 | __interrupt void ADC12ISR (void)
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32 | {
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33 | static unsigned int index = 0;
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34 |
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35 | switch(__even_in_range(ADC12IV,34))
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36 | {
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37 | case 0: break; // Vector 0: No interrupt
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38 | case 2: break; // Vector 2: ADC overflow
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39 | case 4: break; // Vector 4: ADC timing overflow
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40 | case 6: break; // Vector 6: ADC12IFG0
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41 | case 8: break; // Vector 8: ADC12IFG1
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42 | case 10: break; // Vector 10: ADC12IFG2
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43 | case 12: // Vector 12: ADC12IFG3
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44 | A0results[index] = ADC12MEM0; // Move A0 results, IFG is cleared
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45 | A1results[index] = ADC12MEM1; // Move A1 results, IFG is cleared
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46 | A2results[index] = ADC12MEM2; // Move A2 results, IFG is cleared
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47 | A3results[index] = ADC12MEM3; // Move A3 results, IFG is cleared
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48 | index++; // Increment results index, modulo; Set Breakpoint1 here
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49 |
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50 | if (index == 8)
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51 | {
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52 | (index = 0);
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53 | }
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54 | case 14: break; // Vector 14: ADC12IFG4
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55 | case 16: break; // Vector 16: ADC12IFG5
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56 | case 18: break; // Vector 18: ADC12IFG6
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57 | case 20: break; // Vector 20: ADC12IFG7
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58 | case 22: break; // Vector 22: ADC12IFG8
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59 | case 24: break; // Vector 24: ADC12IFG9
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60 | case 26: break; // Vector 26: ADC12IFG10
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61 | case 28: break; // Vector 28: ADC12IFG11
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62 | case 30: break; // Vector 30: ADC12IFG12
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63 | case 32: break; // Vector 32: ADC12IFG13
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64 | case 34: break; // Vector 34: ADC12IFG14
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65 | default: break;
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66 | }
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67 | }
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