Hallo liebe Experten! Ich bin Neuling in VHDL, würde aber gerne wissen, warum ich die Fehlermeldung "Signal sreg_data_in<0> cannot be synthesized, bad synchronous description. erhalte." Könnt Ihr mir bitte bei dem SPI-Interface weiterhelfen? Die Daten kommen parallel und sollen per Load zum Senden losgeschickt werden.
1 | library IEEE; |
2 | use IEEE.STD_LOGIC_1164.ALL; |
3 | use IEEE.STD_LOGIC_ARITH.ALL; |
4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
5 | |
6 | ---- Uncomment the following library declaration if instantiating
|
7 | ---- any Xilinx primitives in this code.
|
8 | --library UNISIM;
|
9 | --use UNISIM.VComponents.all;
|
10 | |
11 | entity spi_exchange_unit is |
12 | generic( -- |
13 | -- data width
|
14 | WIDTH : integer := 8 |
15 | );
|
16 | port( Slow_clk : in STD_LOGIC; |
17 | Data_tx : in STD_LOGIC_VECTOR (7 downto 0); |
18 | Data_rx : out STD_LOGIC_VECTOR (7 downto 0); |
19 | Load : in STD_LOGIC; |
20 | Done : out STD_LOGIC; |
21 | SCK : out STD_LOGIC; |
22 | MOSI : out STD_LOGIC; |
23 | MISO : in STD_LOGIC); |
24 | end spi_exchange_unit; |
25 | |
26 | architecture Behavioral of spi_exchange_unit is |
27 | |
28 | signal sreg_data_in : std_logic_vector(7 downto 0) := (others => '0'); |
29 | signal sreg_data_out : std_logic_vector(7 downto 0) := (others => '0'); |
30 | signal databit_in : integer range 0 to 8 := 0; |
31 | signal databit_out : integer range 0 to 7 := 0; |
32 | |
33 | begin
|
34 | |
35 | SCK <= Slow_clk; |
36 | |
37 | exchange_data : process(Slow_clk, Load, Data_tx, sreg_data_out, sreg_data_in, databit_out, databit_in) |
38 | begin
|
39 | if Load = '1' then |
40 | Done <= '0'; |
41 | sreg_data_out <= Data_tx; |
42 | databit_out <= WIDTH-1; |
43 | databit_in <= WIDTH; |
44 | MOSI <= Data_tx(WIDTH-1); |
45 | end if; |
46 | if falling_edge(Slow_clk) then |
47 | if databit_out > 0 then |
48 | MOSI <= sreg_data_out(databit_out-1); |
49 | databit_out <= databit_out - 1; |
50 | else
|
51 | Done <= '1'; |
52 | MOSI <= '0'; |
53 | Data_rx <= sreg_data_in(WIDTH-1 downto 0); |
54 | end if; |
55 | elsif rising_edge(Slow_clk) then |
56 | if databit_in > 0 then |
57 | sreg_data_in(databit_in-1) <= MISO; |
58 | databit_in <= databit_in - 1; |
59 | end if; |
60 | end if; |
61 | end process exchange_data; |
62 | |
63 | end Behavioral; |
Liebe Grüße Tim