Digitaler Tiefpass VHDL

  LPF: process (Clk, Rst)

    variable sumI, sumQ: signed(baseband_bits-1 downto 0);

    function "sra"(x: signed; n: natural) return signed is

      variable xx: signed(x'length-1 downto 0) := x;

    begin

      for i in 1 to n loop

        xx := xx(xx'left) & xx(xx'left downto 1);

      end loop;

      return xx;

    end;

  begin

    if Rst = '1' then

      filterI <= (others => '0');

      filterq <= (others => '0');

      sumI    := (others => '0');

      sumQ    := (others => '0');

    idumpI  <= (others => '0');

    idumpQ  <= (others => '0');

    elsif rising_edge(Clk) then

      if dump = '1' then -- Dump integrator, generate output

        -- Output lowpass

        filterI <= resize(

                     filterI  + ((signed'((sumI - filterI) * filter_rate)) sra filter_shift),

                     filterI'length);

        filterQ <= resize(

                     filterQ  + ((signed'((sumQ - filterQ) * filter_rate)) sra filter_shift),

                     filterQ'length);

        -- dump the integrator

        sumI := (others => '0');

        sumQ := (others => '0');

      end if;

      -- Integrate (or initialise, if it's the dump cycle)

      sumI := sumI + prodI;

      sumQ := sumQ + prodQ;

      idumpI <= sumI;

      idumpQ <= sumQ;

    end if;

  end process;

  -- Produce the output

  --

  I <= filterI;

  Q <= filterQ;

end;