Hi,
habe gerade dass Problem, dass innerhalb des "generate" Signale
konstant werden und dann von der Synthese entfernt werden.
1 | ps_gen : for I in 1 to C_MAX_PARTICIPANT generate
|
2 | constant C_MAX_PARTDATA : natural := 6;
|
3 | signal readVal_r : natural range 0 to C_MAX_PARTDATA-1;
|
4 |
|
5 | constant c_minVal : natural range 0 to C_MAX_PARTDATA * C_MAX_PARTICIPANT := (I-1)*6;
|
6 | constant c_maxVal : natural range 0 to C_MAX_PARTDATA * C_MAX_PARTICIPANT := I*6;
|
7 | begin
|
8 |
|
9 | p_read: process (rst_n, clk)
|
10 | begin
|
11 | if (rst_n = '0') then
|
12 | readVal_r <= 0;
|
13 | elsif (clk_25'event and clk_25 = '1') then
|
14 | if (Enable = '1') then
|
15 | if (((Value > c_minVal) or (Value = c_minVal)) and ((Value < c_maxVal) or (Value = c_maxVal))) then
|
16 | readVal_r <= natural(Value-c_minVal);
|
17 | else
|
18 | readVal_r <= 0;
|
19 | end if;
|
20 | else
|
21 | readVal_r <= 0;
|
22 | end if;
|
23 | end if;
|
24 | end process;
|
25 |
|
26 | ps: partStat
|
27 | generic map (
|
28 | C_COUNT_WIDTH => C_COUNT_WIDTH)
|
29 | port map (
|
30 | rst_n => rst_n,
|
31 | clk_25 => clk_25,
|
32 | value => readVal_r
|
33 | ..)
|
34 | end generate;
|
Bei der Synthese erhalte ich diese Meldungen.
1 | INFO:Xst:2679 - Register <readVal_r0> in unit <statistic> has a constant value of 000 during circuit operation. The register is replaced by logic.
|
2 | INFO:Xst:2679 - Register <readVal_r1> in unit <statistic> has a constant value of 000 during circuit operation. The register is replaced by logic.
|
3 | INFO:Xst:2679 - Register <readVal_r2> in unit <statistic> has a constant value of 000 during circuit operation. The register is replaced by logic.
|
Leider kann ich mir dies nicht erklären.
Habt Ihr eine Idee?
Matthias
[edit]
Ich habe versehentlich das Eingangssignal "Value" mit
1 | Value : in natural range 0 to 2
|
deklariert, was natürlich falsch ist.
Korrekt ist:
1 | Value : in natural range 0 to 6*C_MAX_PARTICIPANT
|