Hi leute, Ich wollte meine Hauptprogramm, das aus 2 prozessen besteht, mit Testbench überprüfen. aber es ging nicht. das heißt, entweder er mit einem Prozess kompiliert oder mit anderem funktionniert. Kann jemand mir helfen?
> Kann jemand mir helfen? Nein. Ohne deinen Code und am besten deine Testbench geht das nicht. Wir wissen ja nicht mal die Sprache. > aber es ging nicht. Was ging nicht?
Das problem ist, dass der Code lässt sich nicht mit 2 Prozesse (State
machine-process und calc-process) kompilieren. Endweder testbench
funktioniert mit state_machine-process oder mit calc-process. Aber
gleichzeitig nicht.
das ist der code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY correction IS
generic
(
VID_WIDTH : natural := 12;
SHIFT_WRITE_WIDTH : natural := 1;
SHIFT_READ_WIDTH : natural := 2
);
PORT
(
clk : in std_logic;
reset_n : in std_logic;
fval_in : in std_logic;
lval_in : in std_logic;
pval_in : in std_logic;
ref_in : in std_logic_vector(15 downto 0);
ref_out1 : out std_logic_vector(15 downto 0);
ref_out2 : out std_logic_vector(15 downto 0);
ref_out3 : out std_logic_vector(15 downto 0);
ref_out4 : out std_logic_vector(15 downto 0);
fval_out : out std_logic;
lval_out : out std_logic;
pval_out : out std_logic;
rdref : out std_logic
);
END shading_correction;
ARCHITECTURE behavior OF shading_correction IS
signal r_fval : std_logic_vector(SHIFT_WRITE_WIDTH-1 downto 0);
signal r_lval : std_logic_vector(SHIFT_WRITE_WIDTH-1 downto 0);
signal r_pval : std_logic_vector(SHIFT_WRITE_WIDTH-1 downto 0);
signal r_rdref : std_logic_vector(SHIFT_READ_WIDTH-1 downto 0);
signal r2_rdref : std_logic:='0';
signal ref_in1 : std_logic_vector(15 downto 0):=(others => '0');
signal ref_in2 : std_logic_vector(15 downto 0):=(others => '0');
signal ref_in3 : std_logic_vector(15 downto 0):=(others => '0');
signal x : std_logic_vector(7 downto 0):=(others => '0');
signal y : std_logic_vector(7 downto 0):=(others => '0');
signal dx : std_logic_vector(7 downto 0):=(others => '0');
signal dy : std_logic_vector(7 downto 0):=(others => '0');
signal bres_x : std_logic_vector(7 downto 0):=(others => '0');
signal bres_y : std_logic_vector(7 downto 0):=(others => '0');
signal bres_dx : std_logic_vector(7 downto 0):=(others => '0');
signal bres_dy : std_logic_vector(7 downto 0):=(others => '0');
signal next_data_fetch_counter : std_logic_vector(7 downto 0):=(others
=> '0');
signal dir : std_logic :='0';
signal bres_dir : std_logic :='0';
signal bres_set : std_logic :='0';
signal bres_ex : std_logic_vector(7 downto 0):=(others => '0');
signal r_ref_in : unsigned(15 downto 0):=(others => '0');
signal r2_ref_in : unsigned(7 downto 0):=(others => '0');
signal r3_ref_in : unsigned(7 downto 0):=(others => '0');
signal ref_result : std_logic_vector(15 downto 0):=(others => '0');
signal r_mul : std_logic_vector(VID_WIDTH + 8 downto 0);
signal r_sat : std_logic_vector(VID_WIDTH-1 downto 0);
type stm_typ is (IDLE, HOST_RD_FIFO, HOST_RD_DATA_1, HOST_RD_DATA_2,
HOST_RD_DATA_3, HOST_DATA1_DATA2);
signal state : stm_typ ;
BEGIN
ref_out4 <= ref_result;
--vid_out <= r_sat;
fval_out <= r_fval (SHIFT_WRITE_WIDTH-1);
lval_out <= r_lval (SHIFT_WRITE_WIDTH-1);
pval_out <= r_pval (SHIFT_WRITE_WIDTH-1);
rdref <= r2_rdref;
ref_out1 <= ref_in1;
ref_out2 <= ref_in2;
ref_out3 <= ref_in3;
calc: process(reset_n, clk)
begin
if(reset_n = '0') then
r_fval <= conv_std_logic_vector('0', SHIFT_WRITE_WIDTH);
r_lval <= conv_std_logic_vector('0', SHIFT_WRITE_WIDTH);
r_pval <= conv_std_logic_vector('0', SHIFT_WRITE_WIDTH);
r_rdref <= conv_std_logic_vector('0', SHIFT_READ_WIDTH);
ref_in1 <= (others => '0');
ref_in2 <= (others => '0');
r_ref_in <= (others => '0');
r2_ref_in <= x"00";
r3_ref_in <= x"00";
r_mul <= (others => '0');
r_sat <= (others => '0');
r_rdref <= (others => '0');
elsif(clk'event and clk = '1') then
if(bres_set = '1') then
--bres_y <= y;
bres_x <=(others => '0');
bres_dx <= dx;
bres_dy <= dy;
bres_dir <= dir;
bres_ex <= '0' & dx(7 downto 1);
else
bres_x <= bres_x + 1;
if(bres_x = next_data_fetch_counter-3) then
r2_rdref <= '1';
else
r2_rdref <= '0';
end if;
if(bres_ex(7) = '1') then
bres_ex <= bres_ex + bres_dx - bres_dy;
if(bres_dir = '0') then
bres_y <= bres_y + 1;
else
bres_y <= bres_y - 1;
end if;
else
bres_ex <= bres_ex - bres_dy;
end if;
ref_result (7 downto 0) <= bres_x;
ref_result (15 downto 8) <= bres_y;
end if;
end if;
end process;
state_machine: process(reset_n, clk)
begin
if(reset_n = '0') then
r_fval <= conv_std_logic_vector('0', SHIFT_WRITE_WIDTH);
r_lval <= conv_std_logic_vector('0', SHIFT_WRITE_WIDTH);
r_pval <= conv_std_logic_vector('0', SHIFT_WRITE_WIDTH);
r_rdref <= conv_std_logic_vector('0', SHIFT_READ_WIDTH);
ref_in1 <= (others => '0');
ref_in2 <= (others => '0');
r_ref_in <= (others => '0');
r2_ref_in <= x"00";
r3_ref_in <= x"00";
r_mul <= (others => '0');
r_sat <= (others => '0');
r_rdref <= (others => '0');
state <= IDLE;
elsif(clk'event and clk = '1') then
r_fval <= r_fval (SHIFT_WRITE_WIDTH-2 downto 0) & fval_in;
r_lval <= r_lval (SHIFT_WRITE_WIDTH-2 downto 0) & lval_in;
r_pval <= r_pval (SHIFT_WRITE_WIDTH-2 downto 0) & pval_in;
r_rdref <= r_rdref(SHIFT_READ_WIDTH-2 downto 0) & r2_rdref;
case state IS
when IDLE =>
if (lval_in = '0') then
state <= HOST_RD_FIFO;
bres_set <= '0';
end if;
when HOST_RD_FIFO =>
if (lval_in = '1') then
state <= HOST_RD_DATA_1;
r2_rdref <= '1';
bres_set <= '0';
end if;
when HOST_RD_DATA_1 =>
if (r_rdref(SHIFT_READ_WIDTH-2) = '1') then
state <= HOST_RD_DATA_2;
ref_in1 <= (others => '0');
ref_in2 <= ref_in;
r2_rdref <= '0';
bres_set <= '0';
end if;
when HOST_RD_DATA_2 =>
if (r_rdref(SHIFT_READ_WIDTH-1) = '1') then
state <= HOST_DATA1_DATA2;
ref_in1 <= ref_in2;
ref_in2 <= ref_in;
r2_rdref <= '0';
bres_set <= '0';
end if;
when HOST_RD_DATA_3 =>
state <= HOST_DATA1_DATA2;
ref_in1 <= ref_in2;
ref_in2 <= ref_in;
r2_rdref <= '0';
bres_set <= '0';
when HOST_DATA1_DATA2 =>
state <= HOST_RD_DATA_3;
dx <=(ref_in2(7 downto 0));
if(conv_integer(ref_in2(15 downto 8)) > conv_integer(ref_in1(15
downto 8))) then
dy <= ref_in2(15 downto 8) - ref_in1(15 downto 8);
dir <= '0';
else
dy <= ref_in1(15 downto 8) - ref_in2(15 downto 8);
dir <= '1';
end if;
bres_set <= '1';
next_data_fetch_counter <= dx;
end case;
end if;
end process;
END behavior;
TESTBENCH
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------
------------
entity shading_correction_TB is
end shading_correction_TB;
------------------------------------------------------------------------
------------
architecture behavior of shading_correction_TB is
--signal vid_in1 : std_logic_vector(11 downto 0);
signal clk1 : std_logic;
signal reset_n1 : std_logic;
signal fval_in1 : std_logic;
signal lval_in1 : std_logic;
signal pval_in1 : std_logic;
signal ref_in1 : std_logic_vector(15 downto 0);
signal r_ref_in1 : std_logic_vector(15 downto 0);
signal ref_out11 : std_logic_vector(15 downto 0);
signal ref_out21 : std_logic_vector(15 downto 0);
signal ref_out31 : std_logic_vector(15 downto 0);
signal ref_out41 : std_logic_vector(15 downto 0);
--signal vid_out1 : std_logic_vector(11 downto 0);
signal fval_out1 : std_logic;
signal lval_out1 : std_logic;
signal pval_out1 : std_logic;
signal rdref1 : std_logic;
signal i : integer range 0 to 4;
-----------------------------------------------
--signal x_intern1 :unsigned(7 downto 0);
--signal y_intern1 :unsigned(7 downto 0);
--signal x_intern2 :std_logic_vector(7 downto 0);
--signal y_intern2 :std_logic_vector(7 downto 0);
------------------------------------------------------------------------
--------------
--signal x : integer RANGE 0 TO 20;
--signal y : integer RANGE 0 TO 255;
type table_dx is array (0 TO 4) OF INTEGER;
type table_y is array (0 TO 4) OF INTEGER;
constant dx_werte :table_dx:=
(
0, 30, 70, 40, 60
);
constant y_werte :table_y:=
(
100, 110, 90, 75, 80
);
------------------------------------------------------------------------
------------
Component correction
port
(
clk : in std_logic;
reset_n : in std_logic;
fval_in : in std_logic;
lval_in : in std_logic;
pval_in : in std_logic;
ref_in : in std_logic_vector(15 downto 0);
ref_out1 : out std_logic_vector(15 downto 0);
ref_out2 : out std_logic_vector(15 downto 0);
ref_out3 : out std_logic_vector(15 downto 0);
ref_out4 : out std_logic_vector(15 downto 0);
fval_out : out std_logic;
lval_out : out std_logic;
pval_out : out std_logic;
rdref : out std_logic
);
end component;
------------------------------------------------------------------------
------------
for all:correction use entity work.correction(behavior);
------------------------------------------------------------------------
------------
begin
PR_clk: process
begin
clk1 <= '0';
wait for 10 ns;
clk1 <= '1';
wait for 10 ns;
end process PR_clk;
set: process(reset_n1, clk1)
begin
if(reset_n1 = '0') then
fval_in1 <= '0';
lval_in1 <= '0';
pval_in1 <= '0';
elsif(clk1'event and clk1 = '1') then
fval_in1 <= '1';
pval_in1 <= '1';
lval_in1 <= '1';
end if;
end process set;
process(reset_n1, clk1)
begin
if(reset_n1 = '0') then
ref_in1 <= (others => '0');
i <= 0;
elsif(clk1'event and clk1 = '1') then
if(rdref1 = '1') then
r_ref_in1 <= conv_std_logic_vector(y_werte(i), 8) &
conv_std_logic_vector(dx_werte(i), 8);
i <= i+1;
end if;
ref_in1 <= r_ref_in1;
end if;
end process;
------------------------------------------------------------------------
---
reset_n1 <= '0', '1' after 20 ns;
------------------------------------------------------------------------
-----------------------------------
c1: shading_correction port map (clk1, reset_n1, fval_in1, lval_in1,
pval_in1, ref_in1, ref_out11, ref_out21, ref_out31, ref_out41,
fval_out1, lval_out1, pval_out1, rdref1);
------------------------------------------------------------------------
-----------------------------------
end behavior;
>>> aber es ging nicht. >> Was ging nicht? > Das problem ist, dass der Code lässt sich nicht mit 2 Prozesse (State > machine-process und calc-process) kompilieren. Und warum geht es nicht? Was meint der Compiler? Welche Fehlermeldung bekommst du? BTW: Das hier:
1 | r_pval <= conv_std_logic_vector('0', SHIFT_WRITE_WIDTH); |
ist so kürzer und lesbarer:
1 | r_pval <= (others=>'0'); |
BTW2: Hier im Forum kannst du mit [ vdhl ] und [ /vhdl ] (ohne Leerzeichen) den Quelltext schön formatieren lassen
gut danke. ich meine, ich wollte durch den Code in Modelsim die Signale testen, aber es wurde nur die Signale von nur einer der beiden Prozesse erläutert. die andere Signale nicht. Zum Bsp: wenn ich Testbench laufen lasse, bekomme ich die geänderte Signale nur von calc-process und von state_machine-process bekomme ich keines, da bleibt nur die Signale, die von reset_n = '0' unverändert. Es läuft nur bei einem Prozess.
Du kannst nicht von 2 Prozessen auf 1 Signal treiben. Hier mal exemplarisch das Signal r2_rdref:
1 | calc: process(reset_n, clk) |
2 | begin
|
3 | :
|
4 | if(bres_x = next_data_fetch_counter-3) then |
5 | r2_rdref <= '1'; |
6 | :
|
7 | end process; |
8 | |
9 | state_machine: process(reset_n, clk) |
10 | begin
|
11 | :
|
12 | if (lval_in = '1') then |
13 | r2_rdref <= '1'; |
14 | :
|
15 | end process; |
Das passiert, wie ich das sehe, mit den anderen roten Signalen (Zustand X) auch.. Ganz krass ist das hier:
1 | process(reset_n1, clk1) |
2 | begin
|
3 | if(reset_n1 = '0') then |
4 | ref_in1 <= (others => '0'); |
5 | i <= 0; |
6 | elsif(clk1'event and clk1 = '1') then |
7 | if(rdref1 = '1') then |
8 | r_ref_in1 <= conv_std_logic_vector(y_werte(i), 8) & conv_std_logic_vector(dx_werte(i), 8); |
9 | i <= i+1; |
10 | end if; |
11 | |
12 | ref_in1 <= r_ref_in1; -- Sensitivliste des Prozesses unvollständig: r_ref_in1 fehlt!!! |
13 | end if; |
14 | end process; |
Kontrollier erst mal, warum du hier keinen sinnvollen Wert herbekommst.
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