1 | GpioInit();
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2 | // Memory Accelerator Module init
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3 | MAMCR_bit.MODECTRL = 0;
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4 | MAMTIM_bit.CYCLES = 3; // FCLK > 40 MHz
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5 | MAMCR_bit.MODECTRL = 2; // MAM functions fully enabled
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6 | // Init clock
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7 | InitClock();
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8 |
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9 | #define C_GLCD_H_SIZE 640
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10 | #define C_GLCD_H_PULSE 4
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11 | #define C_GLCD_H_FRONT_PORCH 6
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12 | #define C_GLCD_H_BACK_PORCH 6
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13 | #define C_GLCD_V_SIZE 480
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14 | #define C_GLCD_V_PULSE 1
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15 | #define C_GLCD_V_FRONT_PORCH 1
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16 | #define C_GLCD_V_BACK_PORCH 1
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17 | #define C_GLCD_CLK_PER_LINE (C_GLCD_H_SIZE/4 + C_GLCD_H_PULSE + C_GLCD_H_FRONT_PORCH + C_GLCD_H_BACK_PORCH)
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18 | #define C_GLCD_LINES_PER_FRAME (C_GLCD_V_SIZE/2 + C_GLCD_V_PULSE + C_GLCD_V_FRONT_PORCH + C_GLCD_V_BACK_PORCH)
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19 | #define C_GLCD_PIX_CLK (6500000UL)
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20 | #define C_GLCD_ENA_DIS_DLY 10000
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21 |
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22 | #define VGAADDR_U 0x40006a00
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23 | #define VGAADDR_L 0x4000b500
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24 |
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25 | // Init GLCD controller
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26 | PINSEL11_bit.LCDM=2; // 4Bit Mono STN Dual
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27 | PINSEL11_bit.LCDPE=1; // LCD Enabled
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28 | PCONP_bit.PCLCD = 1; // enable LCD controller clock
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29 | CRSR_CTRL_bit.CrsrOn = 0; // Disable cursor
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30 | LCD_CTRL_bit.LcdEn = 0; // disable GLCD controller
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31 | LCD_CTRL_bit.LcdBpp= 0; // 1 bpp
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32 | LCD_CTRL_bit.LcdBW= 1; // monochrome
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33 | LCD_CTRL_bit.LcdTFT= 0; // STN panel
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34 | LCD_CTRL_bit.LcdMono8=0; // 8 Bit Interface
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35 | LCD_CTRL_bit.LcdDual=1; // dual panel
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36 | LCD_CTRL_bit.BGR = 0; // RGB order
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37 | LCD_CTRL_bit.BEBO = 0; // little endian byte order
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38 | LCD_CTRL_bit.BEPO = 0; // little endian pix order
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39 | LCD_CTRL_bit.LcdPwr= 0; // disable power
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40 | LCD_CTRL_bit.LcdVComp=0; // no irq
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41 | LCD_CTRL_bit.WATERMARK=0;
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42 |
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43 | // init pixel clock
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44 | temp=(SYS_GetFsclk() / (Int32U)C_GLCD_PIX_CLK);
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45 | LCD_CFG_bit.CLKDIV = temp;
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46 | LCD_POL_bit.CLKSEL = 0; // clock source for the LCD block is CCLK
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47 | LCD_POL_bit.ACB = 0; // AC Bias not used
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48 | LCD_POL_bit.IVS = 0; // LCDFP pin is active HIGH
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49 | LCD_POL_bit.IHS = 0; // LCDLP pin is active HIGH
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50 | LCD_POL_bit.IPC = 0; // Data is driven out into the LCD on the rising edge
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51 | LCD_POL_bit.IOE = 0; // no Invert Output Enable
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52 | LCD_POL_bit.CPL = C_GLCD_CLK_PER_LINE-1;
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53 | LCD_POL_bit.BCD = 0; // bypass internal clk divider
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54 | LCD_POL_bit.PCD_LO = 6; // Dual Panel Mono: /8
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55 | LCD_POL_bit.PCD_HI = 0;
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56 | // init Horizontal Timing
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57 | LCD_TIMH_bit.HBP = C_GLCD_H_BACK_PORCH - 1;
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58 | LCD_TIMH_bit.HFP = C_GLCD_H_FRONT_PORCH - 1;
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59 | LCD_TIMH_bit.HSW = C_GLCD_H_PULSE - 1;
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60 | LCD_TIMH_bit.PPL = (C_GLCD_H_SIZE/(16*4)) - 1;
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61 | // init Vertical Timing
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62 | LCD_TIMV_bit.VBP = C_GLCD_V_BACK_PORCH;
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63 | LCD_TIMV_bit.VFP = C_GLCD_V_FRONT_PORCH;
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64 | LCD_TIMV_bit.VSW = C_GLCD_V_PULSE;
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65 | LCD_TIMV_bit.LPP = (C_GLCD_V_SIZE/2) - 1;
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66 | // Frame Base Address doubleword aligned
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67 | LCD_UPBASE = VGAADDR_U;
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68 | LCD_LPBASE = VGAADDR_L;
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69 |
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70 | for(volatile Int32U i = C_GLCD_ENA_DIS_DLY; i; i--);
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71 | LCD_CTRL_bit.LcdEn = 1; //Enable LCD
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72 | for(volatile Int32U i = C_GLCD_ENA_DIS_DLY; i; i--);
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73 | LCD_CTRL_bit.LcdPwr= 1; // enable Power
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74 | for(volatile Int32U i = C_GLCD_ENA_DIS_DLY; i; i--);
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75 | FIO1SET=(1<<L_EN_VLCD); // enable VLCD -18V
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