1 | RETCODE I2Cdrv_DMASendData(void* pBuffer, UINT8 NumByteToWrite, UINT8 addr)
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2 | {
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3 |
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4 | /* Check I2C Semaphore */
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5 | OS_Use(&sema);
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6 |
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7 |
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8 | /* Wait while the bus is busy */
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9 | while(I2C_GetFlagStatus(i2cDev, I2C_FLAG_BUSY));
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10 |
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11 | I2C_AcknowledgeConfig(i2cDev, DISABLE);
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12 |
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13 | // Reconfigure DMA
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14 | dmaCfg.DMA_BufferSize = NumByteToWrite;
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15 | DMA_DeInit(TxChannel);
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16 | DMA_Init(TxChannel, &dmaCfg);
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17 |
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18 | DMA_ITConfig(TxChannel, DMA_IT_TC, ENABLE);
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19 | I2C_ITConfig(i2cDev, I2C_IT_EVT, ENABLE);
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20 | I2C_DMACmd(i2cDev, ENABLE);
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21 | // Start
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22 | I2C_GenerateSTART(i2cDev, ENABLE);
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23 |
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24 |
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25 | // Wait EOT iterrupt or I2C Error Status Flags Interrupt
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26 | OS_EVENT_Wait(&event);
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27 |
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28 |
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29 | /* Make sure that the STOP bit is cleared by Hardware before CR1 write access */
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30 | while ((i2cDev->CR1&0x200) == 0x200);
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31 |
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32 | OS_Unuse(&sema);
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33 |
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34 | return NO_ERROR;
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35 | }
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36 |
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37 |
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38 | void I2Cdrv_DMA_TX_ISR()
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39 | {
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40 | DMA_Cmd(TxChannel, DISABLE);
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41 | DMA_ClearFlag(dmaTxFlag);
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42 | }
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43 |
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44 |
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45 | void I2Cdrv_EV1_ISR()
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46 | {
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47 |
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48 | switch (I2C_GetLastEvent(i2cDev))
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49 | {
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50 | case I2C_EVENT_MASTER_MODE_SELECT: /* EV5 */
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51 |
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52 | if( Send_Receive )
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53 | {
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54 | // Send slave Address for write
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55 | I2C_Send7bitAddress(i2cDev, Addr, I2C_Direction_Transmitter);
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56 | }
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57 | else
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58 | {
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59 | // Send slave Address for read
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60 | I2C_Send7bitAddress(i2cDev, Addr, I2C_Direction_Receiver);
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61 | }
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62 | break;
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63 |
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64 | /* Test on I2C1 EV6 and first EV8 and clear them */
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65 | case I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED:
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66 |
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67 | DMA_Cmd(TxChannel, ENABLE);
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68 | break;
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69 |
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70 | // EV8
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71 | case I2C_EVENT_MASTER_BYTE_TRANSMITTING:
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72 | break;
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73 |
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74 | case I2C_EVENT_MASTER_BYTE_TRANSMITTED:
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75 | // I2C STOP Condition
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76 | i2cDev->CR1 |= 0x200;
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77 | // Avoid additional BTF interrupt
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78 | I2C_ITConfig(i2cDev, I2C_IT_EVT, DISABLE);
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79 | // Signal that Transfer is finished
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80 | OS_EVENT_Set(&event);
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81 | break;
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82 |
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83 | case I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED:
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84 | // Start receiving Data over DMA
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85 | DMA_Cmd(RxChannel, ENABLE);
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86 | break;
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87 |
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88 | default:
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89 | break;
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90 | }
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91 |
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92 | }
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