FIFO-Core einbinden/empty project file

[Echo (Gast)]

Moin,

Ich arbeite mit ISE-Webpack 12.3 und nem Spartan 3ES100.
Ich versuche jetzt schon seit einiger Zeit einen FIFO-Core, den ich mit 
Core-Gen selbst erstellt habe, in meinen Code einzubinden. Allerdings 
lautet die aktuelle Fehlermeldung "ERROR:Xst:2369 - Empty project file 
##.prj".

Ich bin, wie in der Hilfe angegeben, verfahren und habe COMPONENT 
Declaration und INSTANTIATION Template in meinen Code eingefügt. Ich 
habe auch entsprechend die Pinbezeichnungen geändert, das UCF-File und 
das NGC-File sind auch ins Projekt eingebunden. Das NGC-File ist direkt 
eingebunden, sonst meckert er das er keine Pin-Zuweisungen hat und er 
nicht routen wird.

Ich hänge mal hier den Hauptcode und das UCF-File an:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib;
ENTITY FIFO_8Bit_test IS
  port (
  clk1: IN std_logic;
  srst1: IN std_logic;
  din1: IN std_logic_VECTOR(7 downto 0);
  wr_en1: IN std_logic;
  rd_en1: IN std_logic;
  dout1: OUT std_logic_VECTOR(7 downto 0);
  full1: OUT std_logic;
  almost_full1: OUT std_logic;
  wr_ack1: OUT std_logic;
  overflow1: OUT std_logic;
  empty1: OUT std_logic;
  almost_empty1: OUT std_logic;
  valid1: OUT std_logic;
  underflow1: OUT std_logic;
  data_count1: OUT std_logic_VECTOR(7 downto 0));
END FIFO_8Bit_test;

ARCHITECTURE use_core OF FIFO_8Bit_test IS

component FIFO_8Bit_test
  port (
  clk: IN std_logic;
  srst: IN std_logic;
  din: IN std_logic_VECTOR(7 downto 0);
  wr_en: IN std_logic;
  rd_en: IN std_logic;
  dout: OUT std_logic_VECTOR(7 downto 0);
  full: OUT std_logic;
  almost_full: OUT std_logic;
  wr_ack: OUT std_logic;
  overflow: OUT std_logic;
  empty: OUT std_logic;
  almost_empty: OUT std_logic;
  valid: OUT std_logic;
  underflow: OUT std_logic;
  data_count: OUT std_logic_VECTOR(7 downto 0));
end component;

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of FIFO_8Bit_test: component is true;

Begin

FIFO_8Bit_test1 : FIFO_8Bit_test
    port map (
      clk => clk1,
      srst => srst1,
      din => din1,
      wr_en => wr_en1,
      rd_en => rd_en1,
      dout => dout1,
      full => full1,
      almost_full => almost_full1,
      wr_ack => wr_ack1,
      overflow => overflow1,
      empty => empty1,
      almost_empty => almost_empty1,
      valid => valid1,
      underflow => underflow1,
      data_count => data_count1);

end use_core;

UCF-File:

NET "clk1" LOC = "M6";
NET "clk1" CLOCK_DEDICATED_ROUTE = FALSE;

NET "rst1" LOC = "G12";  # Bank = 2, Signal name = SW0
NET "rd_en1" LOC = "C11" ;
NET "wr_en1" LOC = "M4" ;

NET "din(0)1" LOC = "N3" ;
NET "din(1)1" LOC = "E2" ;
NET "din(2)1" LOC = "F3" ;
NET "din(3)1" LOC = "G3" ;
NET "din(4)1" LOC = "B4" ;
NET "din(5)1" LOC = "K3" ;
NET "din(6)1" LOC = "L3" ;
NET "din(7)1" LOC = "P11" ;

NET "full1" LOC = "A9" ;
NET "almost_full1" LOC = "B9" ;
NET "wr_ack1" LOC = "A10" ;
NET "overflow1" LOC = "C9" ;
NET "empty1" LOC = "C12" ;
NET "almost_empty1" LOC = "A13" ;
NET "valid1" LOC = "C13" ;
NET "underflow1" LOC = "D12" ;

NET "data_count(0)1" LOC = "G1" ;
NET "data_count(1)1" LOC = "P4" ;
NET "data_count(2)1" LOC = "N4" ;
NET "data_count(3)1" LOC = "N5" ;
NET "data_count(4)1" LOC = "P6" ;
NET "data_count(5)1" LOC = "P7" ;
NET "data_count(6)1" LOC = "M11" ;
NET "data_count(7)1" LOC = "M5" ;

NET "dout(0)1" LOC = "B2" ;
NET "dout(1)1" LOC = "A3" ;
NET "dout(2)1" LOC = "J3" ;
NET "dout(3)1" LOC = "B5" ;
NET "dout(4)1" LOC = "C6" ;
NET "dout(5)1" LOC = "B6" ;
NET "dout(6)1" LOC = "C5" ;
NET "dout(7)1" LOC = "B7" ;

Das .prj-File weswegen er momentan meckert ist leer.

Wäre sehr nett wenn mir damit jemand helfen könnte.

MfG Echo

[Echo (Gast)]

Hat sich erledigt. Hab statt des Core-Gen-Moduls den Code von Herrn 
Miller nutzen können.