Danke, Leute!
Ich hab den Fehler gefunden! :-)
Danke Lothar fuer den Tip... ich hab den trigger eine Instanz
hoeher ueberschrieben, sodass der Ausgang q undefiniert ist,
wenn das Monoflop noch zaehlt.
Ja, aufraeumen ist da auch noetig.
Kaum macht man drei Jahre lang nichts mehr mit dem Zeugs...
Einen schoenen Gruss,
Clemens
Anbei der ueberarbeitete und funktionierende Code:
1 | ---------------------------------------------------------------------------
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2 | -- monoflop.vhd
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3 | -- retriggerable monoflop, adjustable pulse length
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4 | ---------------------------------------------------------------------------
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5 | -- simcheck 20070426, 20101222
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6 |
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7 | library ieee;
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8 | use ieee.std_logic_1164.all;
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9 |
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10 | entity monoflop is
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11 | generic(len : natural := 10); -- stretch a pulse to len
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12 | port(
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13 | clk : in std_logic;
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14 | reset : in std_logic;
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15 | trigger : in std_logic;
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16 | q : out std_logic);
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17 | end monoflop;
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18 |
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19 | architecture arch of monoflop is
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20 | begin
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21 | process (clk, reset)
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22 | variable count : natural range 0 to len;
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23 | begin
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24 | if reset = '1' then
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25 | count := len; -- stop
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26 | q <= '0';
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27 | elsif rising_edge(clk) then
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28 | if trigger = '1' then
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29 | q <= '1';
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30 | count := 1; -- start at 1 for exact timing!
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31 | elsif count < len then
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32 | q <= '1';
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33 | count := count + 1;
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34 | else
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35 | q <= '0';
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36 | end if;
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37 | end if;
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38 | end process;
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39 | end arch;
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... und die Testbench:
1 | ---------------------------------------------------------------------------
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2 | -- monoflop_t.vhd
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3 | -- monoflop testbench
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4 | ---------------------------------------------------------------------------
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5 | -- simcheck 20070426, 20101222
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6 |
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7 | library IEEE;
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8 | use IEEE.std_logic_1164.all;
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9 |
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10 | entity monoflop_t is
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11 | end monoflop_t;
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12 |
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13 | architecture arch of monoflop_t is
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14 |
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15 | component monoflop
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16 | generic (len : natural := 16); -- stretch pulse to len
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17 | port(
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18 | clk : in std_logic;
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19 | reset : in std_logic;
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20 | trigger : in std_logic;
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21 | q : out std_logic);
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22 | end component;
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23 |
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24 | signal clk : std_logic := '1'; -- have rising clk on even time boundaries
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25 | signal reset : std_logic;
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26 | signal trigger : std_logic := '0';
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27 | signal q : std_logic;
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28 |
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29 | begin
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30 |
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31 | dut : monoflop port map(clk, reset, trigger, q);
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32 |
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33 | clock : process
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34 | begin
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35 | wait for 5 ns; clk <= not clk; -- 100MHz clock
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36 | end process clock;
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37 |
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38 | init : process
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39 | begin
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40 | reset <= '0';
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41 | wait for 25 ns;
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42 | reset <= '1';
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43 | wait for 72 ns;
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44 | reset <= '0';
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45 | wait;
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46 | end process init;
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47 |
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48 | trig : process
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49 | begin
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50 | wait for (1 us - 1 ns);
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51 | trigger <= '1';
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52 | wait for 20 ns;
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53 | trigger <= '0';
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54 | wait for (1 us - 3 ns);
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55 | trigger <= '1';
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56 | wait for 2 us + 5 ns;
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57 | trigger <= '0';
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58 | end process trig;
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59 |
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60 | end arch;
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