CRC-Berechnung - Benötige Hilfe bei der Fehlerfindung

                                       -- Testbench

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

-- Leere entity

entity mein_DUT_tb is

generic (

    gDatenlaenge  : integer :=8;

  gCRCLaenge    : integer :=8);

end entity mein_DUT_tb ;

architecture Verhalten of mein_DUT_tb is

 -- Moduldeklaration

COMPONENT  crc 

port (

  data_in  : in std_logic_vector (gDatenlaenge - 1 downto 0);

    crc_en   : in std_logic;

  rst    : in std_logic;

  clk    : in std_logic;

    crc_out : out std_logic_vector (gCRCLaenge - 1 downto 0));

end component;

signal    data_in  :  std_logic_vector (gDatenlaenge - 1 downto 0):= (others =>'0');  

signal    crc_en   :  std_logic  :='0';

signal    rst    :  std_logic  :='0';

signal    clk    :  std_logic  :='0';

signal    crc_out  :  std_logic_vector (gCRCLaenge - 1 downto 0):= (others =>'0');  

procedure Testdaten_anlegen 

(

signal crc_en  : out  std_logic;

signal rst    : out  std_logic

) is

begin

  --wait until rising_edge(clk);

  crc_en<= '1';

  wait until rising_edge(clk);

  wait until rising_edge(clk);

  crc_en<= '0';

  rst<='1';

  wait until rising_edge(clk);

  rst<='0';

  wait until rising_edge(clk);

end Testdaten_anlegen ;

--0000010110001100

begin

  clk   <= not clk  after 20 ns;  -- 25 MHz Taktfrequenz

 CRC_berechnen: process 

  begin  

      rst <= '1';

    wait until rising_edge(clk);

      rst <= '0';

    wait until rising_edge(clk);

  data_in <= conv_std_logic_vector((163),gDatenlaenge);  Testdaten_anlegen (crc_en => crc_en, rst => rst);  

  for I in 0 to 255 loop

    data_in <= conv_std_logic_vector((I),gDatenlaenge);  Testdaten_anlegen (crc_en => crc_en, rst => rst);

    end loop;

 wait until rising_edge(clk);

  crc_en<= '1';

  wait until rising_edge(clk);

  crc_en<= '0';

  wait until rising_edge(clk);

end process;

  -- Modulinstatziierung

  mein_dut : crc

  port map (

   data_in    =>    data_in,

  crc_en     =>    crc_en,

  rst      =>    rst,

  clk      =>    clk,

  crc_out    =>    crc_out            

  );

end architecture;

-------------------------------------------------------------------------------

-- Link zum Generieren des Files: http://outputlogic.com/?page_id=321

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

-- Ports

-- data_in    : Paralleler Eingang der Daten

-- crc_en    : Startsignal

-- rst      : Reset

-- clk      : CLK-Signal

-- crc_out    : Paralleler Ausgang an dem die berechnete CRC bereitgestellt wird

-------------------------------------------------------------------------------

-- Copyright (C) 2009 OutputLogic.com

-- This source file may be used and distributed without restriction

-- provided that this copyright statement is not removed from the file

-- and that any derivative work contains the original copyright notice

-- and the associated disclaimer.

-- 

-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS

-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED

-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.

-------------------------------------------------------------------------------

-- CRC module for data(7:0)

--   lfsr(7:0)=1+x^2+x^3+x^4+x^8;

-------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

entity crc is

  port ( data_in : in std_logic_vector (7 downto 0);

    crc_en , rst, clk : in std_logic;

    crc_out : out std_logic_vector (7 downto 0));

end crc;

architecture imp_crc of crc is

  signal lfsr_q: std_logic_vector (7 downto 0);

  signal lfsr_c: std_logic_vector (7 downto 0);

begin

    crc_out <= lfsr_q;

    lfsr_c(0) <= lfsr_q(0) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(6) xor data_in(0) xor data_in(4) xor data_in(5) xor data_in(6);

    lfsr_c(1) <= lfsr_q(1) xor lfsr_q(5) xor lfsr_q(6) xor lfsr_q(7) xor data_in(1) xor data_in(5) xor data_in(6) xor data_in(7);

    lfsr_c(2) <= lfsr_q(0) xor lfsr_q(2) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(7) xor data_in(0) xor data_in(2) xor data_in(4) xor data_in(5) xor data_in(7);

    lfsr_c(3) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(3) xor lfsr_q(4) xor data_in(0) xor data_in(1) xor data_in(3) xor data_in(4);

    lfsr_c(4) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(2) xor lfsr_q(6) xor data_in(0) xor data_in(1) xor data_in(2) xor data_in(6);

    lfsr_c(5) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(3) xor lfsr_q(7) xor data_in(1) xor data_in(2) xor data_in(3) xor data_in(7);

    lfsr_c(6) <= lfsr_q(2) xor lfsr_q(3) xor lfsr_q(4) xor data_in(2) xor data_in(3) xor data_in(4);

    lfsr_c(7) <= lfsr_q(3) xor lfsr_q(4) xor lfsr_q(5) xor data_in(3) xor data_in(4) xor data_in(5);

    process (clk,rst) begin

      if (rst = '1') then

        lfsr_q <= b"11111111";

      elsif (clk'EVENT and clk = '1') then

        if (crc_en = '1') then

          lfsr_q <= lfsr_c;

        end if;

      end if;

    end process;

end architecture imp_crc;