Forum: FPGA, VHDL & Co. Rocket IO TXUSRCLK


Rocket IO TXUSRCLK
von Harry (Gast)

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Liebe Kollegen!

Ich habe einen Xlinx Rocket IO in meinem Design. Er funktioniert in der 
Simulation (sendet mit der richtigen Rate) aber leider sendet er nur 7 
von 20 Bits. Ich vermute ich habe bei der CLK etwas falsch gemacht. Kann 
mir vielleicht jemand helfen?

Senderate: 1,5 Gbps
RefClk (im Core Generator eingestellt): 75MHz
SysClk: 100 MHZ


die 150 MHz kommen von 1,5Gbps/10=150MHz.

D A N K E ! ! !
Harald

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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.numeric_std.all;

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library UNISIM;

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use UNISIM.VCOMPONENTS.ALL;

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-- Uncomment the following library declaration if using

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-- arithmetic functions with Signed or Unsigned values

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--use IEEE.NUMERIC_STD.ALL;

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-- Uncomment the following library declaration if instantiating

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-- any Xilinx primitives in this code.

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--library UNISIM;

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--use UNISIM.VComponents.all;

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entity Top is

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  port (  

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   Reset              : in   std_logic;

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   clk                : in   std_logic;

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   TILE0_TXN0_OUT                          : out  std_logic;

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    TILE0_TXN1_OUT                          : out  std_logic;

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    TILE0_TXP0_OUT                          : out  std_logic;

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    TILE0_TXP1_OUT                          : out  std_logic;

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   TILE0_RXN0_IN             : in   std_logic;

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    TILE0_RXN1_IN             : in   std_logic;

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    TILE0_RXP0_IN             : in   std_logic;

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    TILE0_RXP1_IN             : in   std_logic

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);   

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end Top;

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architecture Behavioral of Top is

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  signal s_TILE0_RXDATA0_OUT                       :   std_logic_vector(19 downto 0);

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  signal s_TILE0_RXDATA1_OUT                       :   std_logic_vector(19 downto 0);

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  signal s_TILE0_PLLLKDET_OUT                      :   std_logic;

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  signal s_TILE0_REFCLKOUT_OUT                     :   std_logic;

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  signal s_TILE0_RESETDONE0_OUT                    :   std_logic;

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  signal s_TILE0_RESETDONE1_OUT                    :   std_logic;

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  signal s_TILE0_TXOUTCLK0_OUT                     :   std_logic;

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  signal s_TILE0_TXOUTCLK1_OUT                     :   std_logic;

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  signal s_TILE0_TXDATA0_IN                        :   std_logic_vector(19 downto 0);

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  signal s_TILE0_TXDATA1_IN                        :   std_logic_vector(19 downto 0);

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  signal s_clk_75                                  :   std_logic;

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  signal s_clk_150                                 :   std_logic;

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component R_IO 

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generic

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(

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    -- Simulation attributes

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    WRAPPER_SIM_GTPRESET_SPEEDUP    : integer   := 0; -- Set to 1 to speed up sim reset

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    WRAPPER_SIM_PLL_PERDIV2         : bit_vector:= x"14d" -- Set to the VCO Unit Interval time

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);

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port

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(

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    --_________________________________________________________________________

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    --_________________________________________________________________________

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    --TILE0  (Location)

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    --------------- Receive Ports - Comma Detection and Alignment --------------

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    TILE0_RXENPCOMMAALIGN0_IN               : in   std_logic;

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    TILE0_RXENPCOMMAALIGN1_IN               : in   std_logic;

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    ------------------- Receive Ports - RX Data Path interface -----------------

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    TILE0_RXDATA0_OUT                       : out  std_logic_vector(19 downto 0);

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    TILE0_RXDATA1_OUT                       : out  std_logic_vector(19 downto 0);

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    TILE0_RXUSRCLK0_IN                      : in   std_logic;

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    TILE0_RXUSRCLK1_IN                      : in   std_logic;

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    TILE0_RXUSRCLK20_IN                     : in   std_logic;

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    TILE0_RXUSRCLK21_IN                     : in   std_logic;

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    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------

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    TILE0_RXN0_IN                           : in   std_logic;

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    TILE0_RXN1_IN                           : in   std_logic;

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    TILE0_RXP0_IN                           : in   std_logic;

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    TILE0_RXP1_IN                           : in   std_logic;

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    --------------------- Shared Ports - Tile and PLL Ports --------------------

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    TILE0_CLKIN_IN                          : in   std_logic;

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    TILE0_GTPRESET_IN                       : in   std_logic;

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    TILE0_PLLLKDET_OUT                      : out  std_logic;

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    TILE0_REFCLKOUT_OUT                     : out  std_logic;

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    TILE0_RESETDONE0_OUT                    : out  std_logic;

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    TILE0_RESETDONE1_OUT                    : out  std_logic;

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    ------------------ Transmit Ports - TX Data Path interface -----------------

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    TILE0_TXDATA0_IN                        : in   std_logic_vector(19 downto 0);

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    TILE0_TXDATA1_IN                        : in   std_logic_vector(19 downto 0);

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    TILE0_TXOUTCLK0_OUT                     : out  std_logic;

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    TILE0_TXOUTCLK1_OUT                     : out  std_logic;

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    TILE0_TXUSRCLK0_IN                      : in   std_logic;

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    TILE0_TXUSRCLK1_IN                      : in   std_logic;

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    TILE0_TXUSRCLK20_IN                     : in   std_logic;

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    TILE0_TXUSRCLK21_IN                     : in   std_logic;

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    --------------- Transmit Ports - TX Driver and OOB signalling --------------

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    TILE0_TXDIFFCTRL0_IN                    : in   std_logic_vector(2 downto 0);

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    TILE0_TXDIFFCTRL1_IN                    : in   std_logic_vector(2 downto 0);

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    TILE0_TXN0_OUT                          : out  std_logic;

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    TILE0_TXN1_OUT                          : out  std_logic;

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    TILE0_TXP0_OUT                          : out  std_logic;

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    TILE0_TXP1_OUT                          : out  std_logic;

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    TILE0_TXPREEMPHASIS0_IN                 : in   std_logic_vector(2 downto 0);

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    TILE0_TXPREEMPHASIS1_IN                 : in   std_logic_vector(2 downto 0)

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);

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end component;

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  COMPONENT clk_wiz

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  PORT(

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    CLKIN1_IN : IN std_logic;

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    RST_IN : IN std_logic;          

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    CLKOUT0_OUT : OUT std_logic;

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    CLKOUT1_OUT : OUT std_logic

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    );

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  END COMPONENT;

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component Data 

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    Port ( clk : in  STD_LOGIC;

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           reset : in  STD_LOGIC;

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           txdata0 : out  STD_LOGIC_VECTOR (19 downto 0);

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           txdata1 : out  STD_LOGIC_VECTOR (19 downto 0);

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           rxdata0 : in  STD_LOGIC_VECTOR (19 downto 0);

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           rxdata1 : in  STD_LOGIC_VECTOR (19 downto 0));

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end component;

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begin

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----------------------------- The GTP Wrapper -----------------------------

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    r_io_i : R_IO

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    generic map

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    (

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        WRAPPER_SIM_GTPRESET_SPEEDUP    =>      1,

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        WRAPPER_SIM_PLL_PERDIV2         =>      x"14d"

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    )

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    port map

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    (

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        --_____________________________________________________________________

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        --_____________________________________________________________________

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        --TILE0  (X0Y0)

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        --------------- Receive Ports - Comma Detection and Alignment --------------

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        TILE0_RXENPCOMMAALIGN0_IN       =>      '0',

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        TILE0_RXENPCOMMAALIGN1_IN       =>      '0',

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        ------------------- Receive Ports - RX Data Path interface -----------------

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        TILE0_RXDATA0_OUT               =>      s_TILE0_RXDATA0_OUT,

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        TILE0_RXDATA1_OUT               =>      s_TILE0_RXDATA1_OUT,

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      TILE0_RXUSRCLK0_IN              =>      '0',

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        TILE0_RXUSRCLK1_IN              =>      '0',

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        TILE0_RXUSRCLK20_IN             =>      '0',

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        TILE0_RXUSRCLK21_IN             =>      '0',

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        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------

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        TILE0_RXN0_IN                   =>      TILE0_RXN0_IN,

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        TILE0_RXN1_IN                   =>      TILE0_RXN1_IN,

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        TILE0_RXP0_IN                   =>      TILE0_RXP0_IN,

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        TILE0_RXP1_IN                   =>      TILE0_RXP1_IN,

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        --------------------- Shared Ports - Tile and PLL Ports --------------------

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        TILE0_CLKIN_IN                  =>      s_clk_75,

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        TILE0_GTPRESET_IN               =>      reset,

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        TILE0_PLLLKDET_OUT              =>      s_TILE0_PLLLKDET_OUT,

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        TILE0_REFCLKOUT_OUT             =>      s_TILE0_REFCLKOUT_OUT,

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        TILE0_RESETDONE0_OUT            =>      s_TILE0_RESETDONE0_OUT,

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        TILE0_RESETDONE1_OUT            =>      s_TILE0_RESETDONE1_OUT,

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        ------------------ Transmit Ports - TX Data Path interface -----------------

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        TILE0_TXDATA0_IN                =>      s_TILE0_TXDATA0_IN,

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        TILE0_TXDATA1_IN                =>      s_TILE0_TXDATA1_IN,

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        TILE0_TXOUTCLK0_OUT             =>      s_TILE0_TXOUTCLK0_OUT,

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        TILE0_TXOUTCLK1_OUT             =>      s_TILE0_TXOUTCLK1_OUT,

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        TILE0_TXUSRCLK0_IN              =>      s_clk_150,

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        TILE0_TXUSRCLK1_IN              =>      s_clk_150,

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        TILE0_TXUSRCLK20_IN             =>      s_clk_150,

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        TILE0_TXUSRCLK21_IN             =>      s_clk_150,

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        --------------- Transmit Ports - TX Driver and OOB signalling --------------

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        TILE0_TXDIFFCTRL0_IN            =>      "000",

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        TILE0_TXDIFFCTRL1_IN            =>      "000",

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        TILE0_TXN0_OUT                  =>      TILE0_TXN0_OUT,

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        TILE0_TXN1_OUT                  =>      TILE0_TXN1_OUT,

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        TILE0_TXP0_OUT                  =>      TILE0_TXP0_OUT,

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        TILE0_TXP1_OUT                  =>      TILE0_TXP1_OUT,

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        TILE0_TXPREEMPHASIS0_IN         =>      "000",

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        TILE0_TXPREEMPHASIS1_IN         =>      "000"

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    );

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Inst_clk_wiz: clk_wiz PORT MAP(

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    CLKIN1_IN => clk,

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    RST_IN => reset,

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    CLKOUT0_OUT => s_clk_75,

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      CLKOUT1_OUT => s_clk_150    

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  );

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Inst_data : data Port Map(

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        clk => s_clk_75,

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           reset => reset,

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           txdata0 => s_TILE0_TXDATA0_IN,

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           txdata1 => s_TILE0_TXDATA1_IN,

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           rxdata0 => s_TILE0_RXDATA0_OUT,

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           rxdata1 => s_TILE0_RXDATA1_OUT

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);

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end Behavioral;


  


  




  

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    Re: Rocket IO TXUSRCLK
  


  

    

      von
      
        Harry (Gast)
      
      


      
    


    

      
    

    

    

  
  


  

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Sorry, hat sich erledigt. Ich hab die CLK falsch eingestellt.

DANKE

  


  




  

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