1 | library ieee;
|
2 | use ieee.std_logic_1164.all;
|
3 | use ieee.numeric_std.all;
|
4 | library UNISIM;
|
5 | use UNISIM.VCOMPONENTS.ALL;
|
6 |
|
7 |
|
8 | -- Uncomment the following library declaration if using
|
9 | -- arithmetic functions with Signed or Unsigned values
|
10 | --use IEEE.NUMERIC_STD.ALL;
|
11 |
|
12 | -- Uncomment the following library declaration if instantiating
|
13 | -- any Xilinx primitives in this code.
|
14 | --library UNISIM;
|
15 | --use UNISIM.VComponents.all;
|
16 |
|
17 | entity Top is
|
18 | port (
|
19 | Reset : in std_logic;
|
20 | clk : in std_logic;
|
21 | TILE0_TXN0_OUT : out std_logic;
|
22 | TILE0_TXN1_OUT : out std_logic;
|
23 | TILE0_TXP0_OUT : out std_logic;
|
24 | TILE0_TXP1_OUT : out std_logic;
|
25 | TILE0_RXN0_IN : in std_logic;
|
26 | TILE0_RXN1_IN : in std_logic;
|
27 | TILE0_RXP0_IN : in std_logic;
|
28 | TILE0_RXP1_IN : in std_logic
|
29 | );
|
30 | end Top;
|
31 |
|
32 | architecture Behavioral of Top is
|
33 |
|
34 |
|
35 | signal s_TILE0_RXDATA0_OUT : std_logic_vector(19 downto 0);
|
36 | signal s_TILE0_RXDATA1_OUT : std_logic_vector(19 downto 0);
|
37 | signal s_TILE0_PLLLKDET_OUT : std_logic;
|
38 | signal s_TILE0_REFCLKOUT_OUT : std_logic;
|
39 | signal s_TILE0_RESETDONE0_OUT : std_logic;
|
40 | signal s_TILE0_RESETDONE1_OUT : std_logic;
|
41 | signal s_TILE0_TXOUTCLK0_OUT : std_logic;
|
42 | signal s_TILE0_TXOUTCLK1_OUT : std_logic;
|
43 | signal s_TILE0_TXDATA0_IN : std_logic_vector(19 downto 0);
|
44 | signal s_TILE0_TXDATA1_IN : std_logic_vector(19 downto 0);
|
45 | signal s_clk_75 : std_logic;
|
46 | signal s_clk_150 : std_logic;
|
47 |
|
48 |
|
49 |
|
50 | component R_IO
|
51 | generic
|
52 | (
|
53 | -- Simulation attributes
|
54 | WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
|
55 | WRAPPER_SIM_PLL_PERDIV2 : bit_vector:= x"14d" -- Set to the VCO Unit Interval time
|
56 | );
|
57 | port
|
58 | (
|
59 |
|
60 | --_________________________________________________________________________
|
61 | --_________________________________________________________________________
|
62 | --TILE0 (Location)
|
63 |
|
64 | --------------- Receive Ports - Comma Detection and Alignment --------------
|
65 | TILE0_RXENPCOMMAALIGN0_IN : in std_logic;
|
66 | TILE0_RXENPCOMMAALIGN1_IN : in std_logic;
|
67 | ------------------- Receive Ports - RX Data Path interface -----------------
|
68 | TILE0_RXDATA0_OUT : out std_logic_vector(19 downto 0);
|
69 | TILE0_RXDATA1_OUT : out std_logic_vector(19 downto 0);
|
70 | TILE0_RXUSRCLK0_IN : in std_logic;
|
71 | TILE0_RXUSRCLK1_IN : in std_logic;
|
72 | TILE0_RXUSRCLK20_IN : in std_logic;
|
73 | TILE0_RXUSRCLK21_IN : in std_logic;
|
74 | ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
|
75 | TILE0_RXN0_IN : in std_logic;
|
76 | TILE0_RXN1_IN : in std_logic;
|
77 | TILE0_RXP0_IN : in std_logic;
|
78 | TILE0_RXP1_IN : in std_logic;
|
79 | --------------------- Shared Ports - Tile and PLL Ports --------------------
|
80 | TILE0_CLKIN_IN : in std_logic;
|
81 | TILE0_GTPRESET_IN : in std_logic;
|
82 | TILE0_PLLLKDET_OUT : out std_logic;
|
83 | TILE0_REFCLKOUT_OUT : out std_logic;
|
84 | TILE0_RESETDONE0_OUT : out std_logic;
|
85 | TILE0_RESETDONE1_OUT : out std_logic;
|
86 | ------------------ Transmit Ports - TX Data Path interface -----------------
|
87 | TILE0_TXDATA0_IN : in std_logic_vector(19 downto 0);
|
88 | TILE0_TXDATA1_IN : in std_logic_vector(19 downto 0);
|
89 | TILE0_TXOUTCLK0_OUT : out std_logic;
|
90 | TILE0_TXOUTCLK1_OUT : out std_logic;
|
91 | TILE0_TXUSRCLK0_IN : in std_logic;
|
92 | TILE0_TXUSRCLK1_IN : in std_logic;
|
93 | TILE0_TXUSRCLK20_IN : in std_logic;
|
94 | TILE0_TXUSRCLK21_IN : in std_logic;
|
95 | --------------- Transmit Ports - TX Driver and OOB signalling --------------
|
96 | TILE0_TXDIFFCTRL0_IN : in std_logic_vector(2 downto 0);
|
97 | TILE0_TXDIFFCTRL1_IN : in std_logic_vector(2 downto 0);
|
98 | TILE0_TXN0_OUT : out std_logic;
|
99 | TILE0_TXN1_OUT : out std_logic;
|
100 | TILE0_TXP0_OUT : out std_logic;
|
101 | TILE0_TXP1_OUT : out std_logic;
|
102 | TILE0_TXPREEMPHASIS0_IN : in std_logic_vector(2 downto 0);
|
103 | TILE0_TXPREEMPHASIS1_IN : in std_logic_vector(2 downto 0)
|
104 |
|
105 |
|
106 | );
|
107 | end component;
|
108 |
|
109 | COMPONENT clk_wiz
|
110 | PORT(
|
111 | CLKIN1_IN : IN std_logic;
|
112 | RST_IN : IN std_logic;
|
113 | CLKOUT0_OUT : OUT std_logic;
|
114 | CLKOUT1_OUT : OUT std_logic
|
115 | );
|
116 | END COMPONENT;
|
117 |
|
118 | component Data
|
119 | Port ( clk : in STD_LOGIC;
|
120 | reset : in STD_LOGIC;
|
121 | txdata0 : out STD_LOGIC_VECTOR (19 downto 0);
|
122 | txdata1 : out STD_LOGIC_VECTOR (19 downto 0);
|
123 | rxdata0 : in STD_LOGIC_VECTOR (19 downto 0);
|
124 | rxdata1 : in STD_LOGIC_VECTOR (19 downto 0));
|
125 | end component;
|
126 |
|
127 | begin
|
128 |
|
129 | ----------------------------- The GTP Wrapper -----------------------------
|
130 |
|
131 |
|
132 | r_io_i : R_IO
|
133 | generic map
|
134 | (
|
135 | WRAPPER_SIM_GTPRESET_SPEEDUP => 1,
|
136 | WRAPPER_SIM_PLL_PERDIV2 => x"14d"
|
137 | )
|
138 | port map
|
139 | (
|
140 | --_____________________________________________________________________
|
141 | --_____________________________________________________________________
|
142 | --TILE0 (X0Y0)
|
143 |
|
144 | --------------- Receive Ports - Comma Detection and Alignment --------------
|
145 | TILE0_RXENPCOMMAALIGN0_IN => '0',
|
146 | TILE0_RXENPCOMMAALIGN1_IN => '0',
|
147 | ------------------- Receive Ports - RX Data Path interface -----------------
|
148 | TILE0_RXDATA0_OUT => s_TILE0_RXDATA0_OUT,
|
149 | TILE0_RXDATA1_OUT => s_TILE0_RXDATA1_OUT,
|
150 | TILE0_RXUSRCLK0_IN => '0',
|
151 | TILE0_RXUSRCLK1_IN => '0',
|
152 | TILE0_RXUSRCLK20_IN => '0',
|
153 | TILE0_RXUSRCLK21_IN => '0',
|
154 | ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
|
155 | TILE0_RXN0_IN => TILE0_RXN0_IN,
|
156 | TILE0_RXN1_IN => TILE0_RXN1_IN,
|
157 | TILE0_RXP0_IN => TILE0_RXP0_IN,
|
158 | TILE0_RXP1_IN => TILE0_RXP1_IN,
|
159 | --------------------- Shared Ports - Tile and PLL Ports --------------------
|
160 | TILE0_CLKIN_IN => s_clk_75,
|
161 | TILE0_GTPRESET_IN => reset,
|
162 | TILE0_PLLLKDET_OUT => s_TILE0_PLLLKDET_OUT,
|
163 | TILE0_REFCLKOUT_OUT => s_TILE0_REFCLKOUT_OUT,
|
164 | TILE0_RESETDONE0_OUT => s_TILE0_RESETDONE0_OUT,
|
165 | TILE0_RESETDONE1_OUT => s_TILE0_RESETDONE1_OUT,
|
166 | ------------------ Transmit Ports - TX Data Path interface -----------------
|
167 | TILE0_TXDATA0_IN => s_TILE0_TXDATA0_IN,
|
168 | TILE0_TXDATA1_IN => s_TILE0_TXDATA1_IN,
|
169 | TILE0_TXOUTCLK0_OUT => s_TILE0_TXOUTCLK0_OUT,
|
170 | TILE0_TXOUTCLK1_OUT => s_TILE0_TXOUTCLK1_OUT,
|
171 | TILE0_TXUSRCLK0_IN => s_clk_150,
|
172 | TILE0_TXUSRCLK1_IN => s_clk_150,
|
173 | TILE0_TXUSRCLK20_IN => s_clk_150,
|
174 | TILE0_TXUSRCLK21_IN => s_clk_150,
|
175 | --------------- Transmit Ports - TX Driver and OOB signalling --------------
|
176 | TILE0_TXDIFFCTRL0_IN => "000",
|
177 | TILE0_TXDIFFCTRL1_IN => "000",
|
178 | TILE0_TXN0_OUT => TILE0_TXN0_OUT,
|
179 | TILE0_TXN1_OUT => TILE0_TXN1_OUT,
|
180 | TILE0_TXP0_OUT => TILE0_TXP0_OUT,
|
181 | TILE0_TXP1_OUT => TILE0_TXP1_OUT,
|
182 | TILE0_TXPREEMPHASIS0_IN => "000",
|
183 | TILE0_TXPREEMPHASIS1_IN => "000"
|
184 |
|
185 |
|
186 | );
|
187 |
|
188 | Inst_clk_wiz: clk_wiz PORT MAP(
|
189 | CLKIN1_IN => clk,
|
190 | RST_IN => reset,
|
191 | CLKOUT0_OUT => s_clk_75,
|
192 | CLKOUT1_OUT => s_clk_150
|
193 | );
|
194 |
|
195 | Inst_data : data Port Map(
|
196 | clk => s_clk_75,
|
197 | reset => reset,
|
198 | txdata0 => s_TILE0_TXDATA0_IN,
|
199 | txdata1 => s_TILE0_TXDATA1_IN,
|
200 | rxdata0 => s_TILE0_RXDATA0_OUT,
|
201 | rxdata1 => s_TILE0_RXDATA1_OUT
|
202 | );
|
203 |
|
204 | end Behavioral;
|
