1 | // DMA Configurations
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2 | typedef enum DMA_INIT_VALUES_enum {
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3 | /***** DMA0 *****/
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4 | DMA0_Config_Control = 0,
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5 | DMA0_Config_Irq_Select = 0,
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6 | DMA0_Config_Irq_Priority = 0,
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7 | DMA0_Config_Irq_enable = 0,
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8 | DMA0_Config_STA_Address = 0,
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9 | DMA0_Config_STB_Address = 0,
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10 | DMA0_Config_PAD_Address = 0,
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11 | DMA0_Config_Count = 0,
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12 |
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13 | /***** DMA1 *****/
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14 | DMA1_Config_Control = 0,
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15 | DMA1_Config_Irq_Select = 0,
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16 | DMA1_Config_Irq_Priority = 0,
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17 | DMA1_Config_Irq_enable = 0,
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18 | DMA1_Config_STA_Address = 0,
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19 | DMA1_Config_STB_Address = 0,
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20 | DMA1_Config_PAD_Address = 0,
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21 | DMA1_Config_Count = 0,
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22 |
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23 |
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24 | /***** DMA2 *****/
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25 | DMA2_Config_Control = 0,
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26 | DMA2_Config_Irq_Select = 0,
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27 | DMA2_Config_Irq_Priority = 0,
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28 | DMA2_Config_Irq_enable = 0,
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29 | DMA2_Config_STA_Address = 0,
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30 | DMA2_Config_STB_Address = 0,
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31 | DMA2_Config_PAD_Address = 0,
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32 | DMA2_Config_Count = 0,
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33 |
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34 |
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35 | /***** DMA3 *****/
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36 | DMA3_Config_Control = 0,
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37 | DMA3_Config_Irq_Select = 0,
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38 | DMA3_Config_Irq_Priority = 0,
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39 | DMA3_Config_Irq_enable = 0,
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40 | DMA3_Config_STA_Address = 0,
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41 | DMA3_Config_STB_Address = 0,
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42 | DMA3_Config_PAD_Address = 0,
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43 | DMA3_Config_Count = 0,
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44 |
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45 |
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46 | /***** DMA4 *****/
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47 | DMA4_Config_Control = 0,
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48 | DMA4_Config_Irq_Select = 0,
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49 | DMA4_Config_Irq_Priority = 0,
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50 | DMA4_Config_Irq_enable = 0,
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51 | DMA4_Config_STA_Address = 0,
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52 | DMA4_Config_STB_Address = 0,
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53 | DMA4_Config_PAD_Address = 0,
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54 | DMA4_Config_Count = 0,
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55 |
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56 |
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57 | /***** DMA5 *****/
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58 | DMA5_Config_Control = 0,
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59 | DMA5_Config_Irq_Select = 0,
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60 | DMA5_Config_Irq_Priority = 0,
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61 | DMA5_Config_Irq_enable = 0,
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62 | DMA5_Config_STA_Address = 0,
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63 | DMA5_Config_STB_Address = 0,
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64 | DMA5_Config_PAD_Address = 0,
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65 | DMA5_Config_Count = 0,
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66 |
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67 | /***** DMA6 *****/
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68 | DMA6_Config_Control = ((DMA_Control_CHEN_disabled << DMA_Control_CHEN_gp) |
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69 | (DMA_Control_SIZE_word << DMA_Control_SIZE_gp) |
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70 | (DMA_Control_DIR_read_peripheral << DMA_Control_DIR_gp) |
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71 | (DMA_Control_HALF_init_irq_full << DMA_Control_HALF_gp) |
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72 | (DMA_Control_NULLW_disabled << DMA_Control_NULLW_gp) |
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73 | (DMA_Control_AMODE_reg_indirect_post << DMA_Control_AMODE_gp) |
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74 | (DMA_Control_MODE_continuous << DMA_Control_MODE_gp)),
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75 | DMA6_Config_Irq_Select = DMA_Irq_IRQSEL_UART2RX,
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76 | DMA6_Config_Irq_Priority = DMA_INT_PRI_1,
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77 | DMA6_Config_Irq_enable = TRUE,
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78 | DMA6_Config_STA_Address = (void*)(DMA_BufferA[DMA6]),
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79 | DMA6_Config_STB_Address = (int*)(DMA_BufferB[DMA6]),
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80 | DMA6_Config_PAD_Address = (&U2RXREG),
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81 | DMA6_Config_Count = 1,
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82 |
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83 | /***** DMA7 *****/
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84 | DMA7_Config_Control = ((DMA_Control_CHEN_disabled << DMA_Control_CHEN_gp) |
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85 | (DMA_Control_SIZE_word << DMA_Control_SIZE_gp) |
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86 | (DMA_Control_DIR_read_peripheral << DMA_Control_DIR_gp) |
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87 | (DMA_Control_HALF_init_irq_full << DMA_Control_HALF_gp) |
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88 | (DMA_Control_NULLW_disabled << DMA_Control_NULLW_gp) |
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89 | (DMA_Control_AMODE_reg_indirect_post << DMA_Control_AMODE_gp) |
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90 | (DMA_Control_MODE_continuous << DMA_Control_MODE_gp)),
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91 | DMA7_Config_Irq_Select = DMA_Irq_IRQSEL_UART2TX,
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92 | DMA7_Config_Irq_Priority = DMA_INT_PRI_1,
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93 | DMA7_Config_Irq_enable = TRUE,
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94 | DMA7_Config_STA_Address = (int)(DMA_BufferA[DMA7]),
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95 | DMA7_Config_STB_Address = (int)(DMA_BufferB[DMA7]),
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96 | DMA7_Config_PAD_Address = (&U2TXREG),
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97 | DMA7_Config_Count = 1
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98 | }DMA_Init_Values;
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99 |
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100 | void hw_Open_DMA6 (void)
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101 | {
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102 | IEC4bits.DMA6IE = 0; // Disable DMA Interrupt
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103 |
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104 | DMA6CON = DMA6_Config_Control;
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105 | DMA6REQ = DMA6_Config_Irq_Select;
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106 | DMA6STA = (unsigned int) Sta_Address - (unsigned int)&_DMA_BASE;
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107 | DMA6STB = (unsigned int) Stb_Address - (unsigned int)&_DMA_BASE;
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108 | DMA6PAD = Pad_Address;
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109 | DMA6CNT = DMA6_Config_Count-1;
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110 |
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111 | IPC17bits.DMA6IP = DMA6_Config_Irq_Priority; // Set DMA Interrupt Priority
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112 | IFS4bits.DMA6IF = 0; // Clear DMA Interrupt Flag
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113 | IEC4bits.DMA6IE = DMA6_Config_Irq_enable; // Enable / Disable DMA Interrupt
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114 | DMA6CONbits.CHEN = 1; // Enable DMA Channel
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115 | }
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