Xplain SDRAM Frage

; SDRAM initialisieren

; läuft so mit 64MHz / 8MB SDRAM "MT48LC16M4A2TG" im "Three-port SDRAM"-Modus

SDRAM1:  ldi  h1, 0x0F

  sts  PORTH_OUT, h1  ; Set signals which are active-low to high value

  ldi  h1, 0xFF    ; Configure bus pins as outputs(except for data lines)

  sts  PORTH_DIR, h1  ; WE, CAS, RAS, DQM, BA0, BA1, CKE, CLK

  sts  PORTK_DIR, h1  ; A[7:0]

  ldi  h1, 0xF0

  sts  PORTJ_DIR, h1  ; A[11:8], D[3:0]

; Initialize EBI

  ldi  h1, 0b00001101  ; 4 bit data bus | EBI enabled with 3-port interface (SRAM: No address multiplexing)

  sts  EBI_CTRL, h1

  ldi  h1,  EBI_SDROW_bm | EBI_SDCOL_10BIT_gc  ; Row addressing A0-A11 (12) | Column addressing A0-A9 (10)

  sts  EBI_SDRAMCTRLA, h1

; Einstellungen S. 48..49 64MHz --> 15,625ns

; MRDLY:    LOAD MODE REGISTER command to ACTIVE or REFRESH command: 2T

; ROWCYCDLY: delay between a Refresh and an Activate command: 3T

; RPDLY:    delay between a Pre-charge command and another command: 20ns --> 2T

; WRDLY:    Write Recovery time: 1 CLK + 7.5 ns --> 2T

; ESRDLY:   Exit Self Refresh to Active Delay: 75ns --> 5T

; ROWCOLDLY: delay between an Activate command and a Read/Write command: 20ns --> 2T

  ldi  h1, 0b10011010  ; 2 CLK PER2 cycles delay, 3 CLK PER2 cycles delay, 2 CLK PER2 cycles delay

  sts  EBI_SDRAMCTRLB, h1

  ldi  h1, 0b10101010  ; 2 CLK PER2 cycles delay, 5 CLK PER2 cycles delay, 2 CLK PER2 cycles delay

  sts  EBI_SDRAMCTRLC, h1

  ldi  h1, 0xE8    ; 15.6µs/row = 64ms --> 0,000015625 * 64000000Hz = 1000

  sts  EBI_REFRESH, h1

  ldi  h1, 0x03

  sts  EBI_REFRESH+1, h1

  ldi  h1, 0x00

  sts  EBI_INITDLY, h1

  ldi  h1, 0x19    ; 100µs --> 0,0001s * 64000000Hz = 6400T

  sts  EBI_INITDLY+1, h1

  ldi  h1, 0b00000000

  sts  EBI_CS3_CTRLB, h1

;  ldi  h1, 0x40    ; BasAddr geht für 8/16kByte AdrSpace

;  ldi  h1, 0x80    ; BasAddr für 32kByte AdrSpace - ansonsten Basisadresse laufend an der Grenze ändern

  ldi  h1, 0x00    ; BasAddr für 8MByte AdrSpace

  sts  EBI_CS3_BASEADDR, h1

;  ldi  h1, 0x00    ; BasAddr geht für 8/16kByte AdrSpace

  ldi  h1, 0x80    ; BasAddr für 8MByte AdrSpace

  sts  EBI_CS3_BASEADDR+1, h1

;  ldi  h1, 0x17    ; AdrSpace 8kByte

;  ldi  h1, 0x1B    ; AdrSpace 16kByte

;  ldi  h1, 0x1F    ; AdrSpace 32kByte

  ldi  h1, 0x3F    ; AdrSpace 8MByte

  sts  EBI_CS3_CTRLA, h1