1 | void HRPWM1_Config(period)
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2 | {
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3 |
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4 | EALLOW;
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5 |
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6 | EPwm1Regs.TBPRD = period/2; // Period = 585,37 TBCLK counts
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7 | EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
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8 |
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9 | EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Symmetrical mode
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10 | EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
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11 | EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
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12 | EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
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13 | EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
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14 | EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
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15 | EPwm1Regs.TBCTL.bit.FREE_SOFT = 3;
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16 |
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17 | EPwm1Regs.ETSEL.bit.SOCAEN = 1;
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18 | EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;
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19 | EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST;
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20 |
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21 | EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
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22 | EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
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23 | EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; // load on CTR=Zero
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24 |
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25 | // EPwm1Regs.AQCTLA.bit.CBU = AQ_SET; // set actions for EPWM1B
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26 | // EPwm1Regs.AQCTLA.bit.CBD = AQ_CLEAR; // if using this one TBPRD = 147
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27 | EPwm1Regs.AQCTLA.bit.ZRO = AQ_TOGGLE;
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28 | EDIS;
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29 | }
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30 |
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31 | void HRPWM3_Config(period)
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32 | {
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33 |
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34 |
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35 | // ePWM3 register configuration with HRPWM
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36 | // ePWM3A toggle high/low with MEP control on falling edge
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37 |
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38 | EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set Immediate load
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39 | EPwm3Regs.TBPRD = period-1; // PWM frequency = 1 / period
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40 | EPwm3Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
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41 | EPwm3Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
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42 | EPwm3Regs.TBPHS.all = 0;
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43 | EPwm3Regs.TBCTR = 0;
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44 |
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45 |
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46 |
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47 | EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
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48 | EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // EPwm3 is the Master
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49 | EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
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50 | EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
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51 | EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
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52 |
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53 | EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
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54 | EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD;
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55 | EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
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56 | EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
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57 |
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58 | EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low
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59 | EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;
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60 | EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET;
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61 | EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR;
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62 |
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63 | EALLOW;
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64 | EPwm3Regs.HRCNFG.all = 0x0;
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65 | EPwm3Regs.HRCNFG.bit.EDGMODE = HR_BEP; //MEP control on falling edge
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66 | EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP;
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67 | EPwm3Regs.HRCNFG.bit.HRLOAD = HR_CTR_PRD;
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68 | EDIS;
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69 | }
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