Hallo zusammen;
Ich habe da folgendes Problem:
Mein VHDL Compiler erkennt die numeric_std nicht:
1 | library IEEE;
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2 | use IEEE.std_logic_1164.all;
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3 | use IEEE.numeric_std.all;
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4 |
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5 | -- Beschreibung der Black Box:
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6 |
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7 | entity d_ff_reg is
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8 | port
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9 | (
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10 | d_i : in std_logic_vector (3 downto 0);
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11 | clk_i : in std_logic;
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12 | en_i : in std_logic;
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13 | sh_i : in std_logic;
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14 | reset : in std_logic;
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15 | q_o : out std_logic_vector (3 downto 0)
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16 | );
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17 | end d_ff_reg;
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18 |
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19 | architecture sim of d_ff_reg is
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20 |
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21 | signal output_holder : std_logic_vector (3 downto 0);
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22 |
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23 | begin
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24 | p_logic0 : process (clk_i, reset)
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25 | begin
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26 | if(reset='1') then
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27 | output_holder <= "0000";
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28 | elsif(clk_i'event and clk_i='1') then
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29 | if(en_i='0' and sh_i='0') then
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30 | output_holder <= output_holder;
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31 | elsif(en_i='0' and sh_i='1') then
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32 | output_holder <= output_holder;
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33 | elsif(en_i='1' and sh_i='0') then
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34 | output_holder <= d_i;
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35 | elsif(en_i='1' and sh_i='1') then
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36 | output_holder <= SHIFT_LEFT(UNSIGNED(output_holder),1);
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37 | end if;
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38 | end if;
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39 | end process p_logic0;
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40 | q_o <= output_holder;
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41 | end sim;
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Warum bekomme ich folgende Fehlermeldung obwohl die packages doch eh
oben eingeblendet sind:
vhd(36): No feasible entries for subprogram "shift_left".
in Zeile:
1 | output_holder <= SHIFT_LEFT(UNSIGNED(output_holder),1);
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vhd(41): VHDL Compiler exiting