Lattice Libraries mit Modelsim kompilieren

Creating the Logical Library (vlib)

Before you can compile your source files, you must create a library in which to store the

compilation results. You can create the logical library using the GUI, by choosing File > New >

Library from the main menu (see Creating a Library), or you can use the vlib command. For

example, the following command:

vlib work

creates a library named work. By default, compilation results are stored in the work library.

Mapping the Logical Work to the Physical Work Directory (vmap)

VHDL uses logical library names that can be mapped to ModelSim library directories. If

libraries are not mapped properly, and you invoke your simulation, necessary components will

not be loaded and simulation will fail. Similarly, compilation can also depend on proper library

mapping.

By default, ModelSim can find libraries in your current directory (assuming they have the right

name), but for it to find libraries located elsewhere, you need to map a logical library name to

the pathname of the library.

You can use the GUI (Library Mappings with the GUI, a command (Library Mapping from the

Command Line), or a project (Getting Started with Projects to assign a logical name to a design

library.

The format for command line entry is:

vmap <logical_name> <directory_pathname>

This command sets the mapping between a logical library name and a directory.