i have a problem with this code... I obtain "Signal rstemp cannot be synthesized, bad synchronous description." thanks.. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity contatore is port ( SET: in STD_LOGIC; RESET: in STD_LOGIC; RST: out STD_LOGIC; LOAD, DIR: in STD_LOGIC; DIN: in STD_LOGIC_VECTOR(3 downto 0); TEST: out STD_LOGIC_VECTOR(3 downto 0)); end contatore; architecture Behavioral of contatore is SIGNAL next_state : std_logic_vector (3 downto 0); begin process(SET, RESET, LOAD, DIN, DIR, next_state) variable count : std_logic_vector (3 downto 0); variable Temp : std_logic_vector (4 downto 0); variable rstemp: STD_LOGIC; begin if (DIR='1') then rstemp:='0'; -- conteggio up case count is when "1001" => next_state<="0000"; when others => next_state<=count+1; end case; end if; if (DIR='0') then -- conteggio down rstemp:='0'; case count is when "0000" => next_state<="1001"; when others => next_state<=count-1; end case; end if; if ((RESET and DIR)='1') then -- Il reset ha priorità massima count:="0000"; elsif (RESET='1' and DIR='0') then count:="1001"; elsif (Load='1') then -- il load ha priorità secondaria count:=DIN; elsif (SET='1' and SET'event) then -- sensibile al fronte di salita di SET count:=next_state; -- conteggia end if; TEST<=count; Temp:= next_state & DIR; if (SET='1' and SET'event) then case Temp is when "00001" => rstemp:='1'; when "10010" => rstemp:='1'; when others => rstemp:='0'; end case; end if; RST<=rstemp; end process; end Behavioral;
Hi, you have to much "If" statements, write all in one: IF () .. ELSIF () .. ELSIF () .. ELSIF () .. . . . ELSE .. END IF;
You work without a clock, why? your programming style isn't so good.
this is asincronous contuer i don't need a clock... who can help me???
Hello Daniele, of course does it need a clock, even it is an asyc. counter! The only difference between the code I wrote for you and this is, that you renamed "clk" to "set" and insert "rstemp:='0'" in the Lookup-tables. You programmed, that rstemp should be "0" for both states of "DIR". This is opposite too: "... case Temp is when "00001" => rstemp:='1'; when "10010" => rstemp:='1'; when others => rstemp:='0'; end case;" Look what "Temp" is: It is a combinition of "nextstate" and "DIR". The last bit of Temp is "DIR"! So the error is that, what the compiler says: "bad describtion", because nobody knows what you want (me too). Henrik
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