Kompilationsproblem

[Finot (Gast)]

Allo,

entschuldigung mich bitte, I spreche deutsch aber nicht so gut. Also
werde ich in english schreiben...

I'm french and just began a University project, I must acquire data
from a CMOS CCD sensor and put them in the FPGA memory.

I have big problems with compilation, because it's veeery long, and
when it compiled (before I used the "loop" statement), I had problems
with the licence:

"Warning: FLEXlm software error: Future license file format or
misspelling in license file..."

Do you have advices for me to go back on the right path?

This is the code I use now:



LIBRARY ieee;
Use iEEE.std_logic_1164.all;
Use ieee.std_logic_arith.all;

ENTITY recup IS
PORT(
VSYNC : IN STD_LOGIC;
PCLK : IN STD_LOGIC;
HREF : IN STD_LOGIC;
Y : IN STD_LOGIC_VECTOR (0 TO 7)
);
END recup;

ARCHITECTURE archi OF recup IS
TYPE Matrice is ARRAY (0 TO 639) of std_logic_vector(0 TO 7);
SIGNAL data : Matrice;
SIGNAL i : integer;

BEGIN
PROCESS(PCLK)
BEGIN

LOOP
EXIT WHEN i=1;

IF (VSYNC'EVENT AND VSYNC='0') THEN
IF (PCLK'EVENT AND PCLK='1') THEN
IF HREF='1' THEN
data(i)<=Y;
i<=i+1;
END IF;
END IF;
END IF;

END LOOP;

END PROCESS;
END archi;



Danke schön.

[Max Müller (Gast)]

Hello Finot,

it seams that you have a license problem to solve before you can go
further with your vhdl code.

Maybe you have the wrong license file or the wrong issue of software
for the license.

If you have solved this problem. The next step seams to correct your
vhdl Code.
You should only use one "'event" condition inside of one process.

Just think about your requirement.
In the upper code you expact a falling edge on vsync and at the same
time a rising edge on PCLK. It is just impossible.

Also your declaration of data with the type Matrice is also a little
bit optimistic. Because with this declaration you need a FPGA with at
least 5112 Flip-Flops. It will be a really big one.

Which FPGA or CPLD do you want to use?
It seams a better Idea to use possible available SRAM-cells like
BLOCKRAM for the storage of the CCD Data.


Regards

Max.

Ich hoffe, das ich nicht in Konflikt mit den Board Regeln durch meine
englischen Antwort komme. Falls ja einfach sagen, dann schreib ich
alles auch noch auf Deutsch :-)

[Finot (Gast)]

OK, then I'll look fot this solutions.

Danke für diese antwort...
Und Ich verstehe deine englisch sehr gut!

[Finot (Gast)]

Now I've got few methods to interface my Cyclone with SDRAM, but the
problem is that I can't get any information on the wiring of the board
I use (NIOS II development kit)!!

Has anybody already worked with that device?

[Jörn (Gast)]

Hi,

look at the Altera homepage. They have good informations about their
development kits. For getting familiar with the kit take their sample
NIOS II configurations.

I use the NIOS II with a Stratix II FPGA.

regards
Jörn

[Max Müller (Gast)]

Maybe you didn't understand my suggestion by the correct way.

It seams also to be overkilled to use external SDRAM for the few Bits
you need for the storage.

There are a lot of FPGA's which have internal SRAM cells.
These SRAM Cells are organised often as dual ported RAM.
With this kind of RAM it is also very simple to convert the bitstream
to a more comfortable format with a organisation of x8 or x16 bits.
Also you can solve the timing generation Problem for the CCD chip.

Regards

Max

[Finot (Gast)]

Hi,

I must storage a compltete picture (664*492 pixels). One pixel takes 8
bits, so the internal RAM of my FPGA (239 ko) is not enough. Don't you
think?

I found an IP that helps me to interface with the 16MB SDRAM of the
board. I think I will go on with that idea. Have you ever used some of
these IPs?

[Jörn (Gast)]

Hi,

what Cyclone FPGA do u use?

[Finot (Gast)]

The exact device is EP1C12F324C6...