von
fred (Gast)
25.10.2012 13:56
Hallo,
Ich bin langsam am verzweifeln. Versuche ein variables IODELAY2 mit
einem Spartan 6 zu realisieren. Als "Testsignal" habe ich einen
counter-process, der das Testsignal toggelt. Das IODELAY ist im
VARIABLE_FROM_ZERO mode und der Counter im OVERFLOW mode. Mit einem
anderen Prozess setze ich das CE-Signal und INC-Signal, was im Grunde
den Zähler im IODELAY2 hochzählen müsste. Das funktioniert jedoch nicht.
Kann mir Jemand weiterhelfen?
Viele Grüße,
Fred
1 library IEEE ;
2 use IEEE . STD_LOGIC_1164 . ALL ;
3 use IEEE . STD_LOGIC_UNSIGNED . ALL ;
4
5 library UNISIM ;
6 use UNISIM . VCOMPONENTS . ALL ;
7
8 entity delay_test is
9 port
10 (
11 REFCLK_PIN : in std_logic ;
12
13 FPGA_RESET : in std_logic ;
14
15 TP1 : out std_logic ;
16 TP2 : out std_logic
17 );
18 end delay_test ;
19
20 architecture Behavioral of delay_test is
21
22 -- DCMs
23 component dcm_master
24 port
25 (
26 CLKIN_IN : in std_logic ;
27 RST_IN : in std_logic ;
28 CLKFX000 : out std_logic
29 );
30 end component ;
31
32 component dcm_clock
33 port
34 (
35 CLKIN_IN : in std_logic ;
36 RST_IN : in std_logic ;
37 CLKDIV : out std_logic ;
38 CLK2X_OUT : out std_logic ;
39 CLKFX000 : out std_logic ;
40 LOCKED_OUT : out std_logic
41 );
42 end component ;
43
44 attribute IOB : string ;
45
46 -- Clocks
47 signal REFCLK : std_logic ;
48 signal PLL_CLK_FB , CMV_CLK_PLL : std_logic ;
49 signal LVDS_CLK_DCM , LVDS_CLK : std_logic ;
50
51 signal clk_32 : std_logic ;
52
53 signal system_reset : std_logic ;
54
55 signal FOO : std_logic ;
56
57 signal dcm_locked : std_logic ;
58
59 signal lvds_clk_iob : std_logic ;
60
61 signal LVDS_CLK_IODELAY_P , LVDS_CLK_IODELAY_N : std_logic ;
62 signal IODELAY_IO_RESET , IODELAY_CLK_RESET : std_logic ;
63 signal DELAY_DATA_CAL : std_logic ;
64
65 signal LVDS_CLK_P , LVDS_CLK_N : std_logic ;
66
67 signal LVDS_DATA_IN_BUF : std_logic ;
68
69 signal LVDS_CH1_IODELAY : std_logic ;
70
71 signal BAR : std_logic ;
72
73 signal I_CE , I_INC : std_logic ;
74
75 type VDELAY_FSM_STATES is (
76 STATUS_SET_CALC ,
77 STATUS_WAIT_CALC ,
78 STATUS_SET_RST ,
79 STATUS_WAIT_DELAY
80 );
81
82 signal VDELAY_FSM_STATE : VDELAY_FSM_STATES ;
83 signal VDELAY_CAL_DELAY : integer range 0 to 66666 ;
84 signal VDELAY_IODELAY_CAL : integer range 0 to 66666 ;
85 signal VDELAY_IODELAY_RST : integer range 0 to 66666 ;
86 signal I_CAL_DELAY : integer range 0 to 66666 ;
87
88 signal I_CAL , I_RST , I_BUSY : std_logic ;
89
90 begin
91 system_reset <= not FPGA_RESET ;
92 REFCLK_BUFG_INST : BUFG port map ( I => REFCLK_PIN , O => REFCLK );
93
94 CMVCLK_INST : PLL_BASE
95 generic map
96 (
97 CLKIN_PERIOD => 20 . 000 ,
98 CLKFBOUT_MULT => 10 ,
99 CLK_FEEDBACK => "CLKFBOUT" ,
100 COMPENSATION => "SYSTEM_SYNCHRONOUS" ,
101
102 CLKOUT0_DIVIDE => 30 , -- MA Takt 100=5Mhz 50=10Mhz 25=20Mhz
103
104 CLKOUT0_PHASE => 0 . 000 ,
105 CLKOUT0_DUTY_CYCLE => 0 . 500
106 )
107 port map
108 (
109 CLKIN => REFCLK ,
110 RST => system_reset ,
111 CLKFBOUT => PLL_CLK_FB ,
112 CLKFBIN => PLL_CLK_FB ,
113
114 CLKOUT0 => CMV_CLK_PLL
115 );
116
117 -----------------------------------
118
119 LVDSCLK_DCM_INST : DCM_SP
120 generic map
121 (
122 CLKIN_PERIOD => 60 . 0 , --50.0, --200.0, -- MA Takt 100=200 50=100 25=50
123 CLKFX_MULTIPLY => 10 ,
124 CLKFX_DIVIDE => 1 ,
125 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS"
126 )
127 port map
128 (
129 CLKIN => CMV_CLK_PLL ,
130 RST => system_reset ,
131 CLKFB => '0' ,
132 DSSEN => '0' ,
133
134 CLK0 => open ,
135 CLKFX => LVDS_CLK_DCM ,
136
137 LOCKED => dcm_locked
138 );
139
140 LVDSCLK_BUFG_INST : BUFG port map ( I => LVDS_CLK_DCM , O => LVDS_CLK );
141
142 LVDS_CLK_ODDR2_INST : ODDR2
143 port map
144 (
145 C0 => "not" ( LVDS_CLK ), C1 => LVDS_CLK , -- FIXME: Phase 180° gedreht ??!!??
146 D0 => '1' , D1 => '0' ,
147 CE => '1' , R => '0' , S => '0' ,
148 Q => LVDS_CLK_IOB
149 );
150
151
152
153 LVDS_CLK_IOB_INST : OBUFDS
154 generic map ( IOSTANDARD => "LVDS_25" )
155 port map ( I => LVDS_CLK_IOB , O => LVDS_CLK_P , OB => LVDS_CLK_N );
156
157
158 cnt : process ( SYSTEM_RESET , REFCLK )
159 variable count : natural range 0 to 500000 ;
160 begin
161 if SYSTEM_RESET = '0' then
162 count : = 0 ;
163 TP2 <= '1' ;
164 elsif rising_edge ( REFCLK ) then
165 if count < 250000 then
166 count : = count + 1 ;
167 TP2 <= '1' ;
168 FOO <= '1' ;
169 elsif count < 500000 then
170 TP2 <= '0' ;
171 FOO <= '0' ;
172 count : = count + 1 ;
173 else
174 count : = 0 ;
175 end if ;
176 end if ;
177 end process cnt ;
178
179
180 cnt2 : process ( SYSTEM_RESET , REFCLK )
181 variable count : natural range 0 to 800000 ;
182 begin
183 if SYSTEM_RESET = '0' then
184 count : = 0 ;
185 elsif rising_edge ( REFCLK ) then
186 if count < 600000 then
187 count : = count + 1 ;
188 I_CE <= '1' ;
189 I_INC <= '1' ;
190 else
191 count : = 0 ;
192 I_CE <= '0' ;
193 I_INC <= '0' ;
194 end if ;
195 end if ;
196 end process cnt2 ;
197
198 -- elsif count < 800000 then
199 -- I_CE <= '0';
200 -- I_INC <= '0';
201 -- count := count + 1;
202
203 cnt3 : process ( SYSTEM_RESET , REFCLK )
204 variable cntr : natural range 0 to 800000 ;
205 begin
206 if SYSTEM_RESET = '0' then
207 cntr : = 0 ;
208 elsif rising_edge ( REFCLK ) then
209 if cntr < 400000 then
210 cntr : = cntr + 1 ;
211 I_CAL <= '1' ;
212 elsif cntr < 800000 then
213 I_CAL <= '0' ;
214 cntr : = cntr + 1 ;
215 else
216 cntr : = 0 ;
217 I_CAL <= '0' ;
218 end if ;
219 end if ;
220 end process cnt3 ;
221
222
223
224
225 IOBUF_NEU_INST : IOBUF
226 port map
227 (
228 I => FOO ,
229 O => LVDS_DATA_IN_BUF ,
230 T => '0' ,
231 IO => open
232 );
233
234 DA_INST : OBUF
235 port map
236 (
237 I => LVDS_CH1_IODELAY ,
238 O => BAR
239 );
240
241 IODELAY2_NEU_INST : IODELAY2
242 generic map (
243 COUNTER_WRAPAROUND => "WRAPAROUND" , -- "STAY_AT_LIMIT" or "WRAPAROUND"
244 DATA_RATE => "SDR" , -- "SDR" or "DDR"
245 DELAY_SRC => "IDATAIN" , -- "IO", "ODATAIN" or "IDATAIN"
246 IDELAY2_VALUE => 0 , -- Delay value when IDELAY_MODE="PCI" (0-255)
247 IDELAY_MODE => "NORMAL" , -- "NORMAL" or "PCI"
248 IDELAY_TYPE => "VARIABLE_FROM_ZERO" , -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
249 -- or "DIFF_PHASE_DETECTOR"
250 IDELAY_VALUE => 0 , -- Amount of taps for fixed input delay (0-255)
251 ODELAY_VALUE => 0 , -- Amount of taps fixed output delay (0-255)
252 SERDES_MODE => "NONE" , -- "NONE", "MASTER" or "SLAVE"
253 SIM_TAPDELAY_VALUE => 75 -- Per tap delay used for simulation in ps
254 )
255 port map (
256 BUSY => I_BUSY , -- 1-bit output: Busy output after CAL
257 DATAOUT => open , -- 1-bit output: Delayed data output to ISERDES/input register
258 DATAOUT2 => LVDS_CH1_IODELAY , -- 1-bit output: Delayed data output to general FPGA fabric
259 DOUT => open , -- 1-bit output: Delayed data output
260 TOUT => open , -- 1-bit output: Delayed 3-state output
261 CAL => I_CAL , -- 1-bit input: Initiate calibration input
262 CE => I_CE , -- 1-bit input: Enable INC input
263 CLK => LVDS_CLK , -- 1-bit input: Clock input
264 IDATAIN => LVDS_DATA_IN_BUF , -- 1-bit input: Data input (connect to top-level port or I/O buffer)
265 INC => I_INC , --DELAY_DATA_INC, -- 1-bit input: Increment / decrement input
266 IOCLK0 => LVDS_CLK , -- 1-bit input: Input from the I/O clock network
267 IOCLK1 => '0' , -- 1-bit input: Input from the I/O clock network
268 ODATAIN => '0' , -- 1-bit input: Output data input from output register or OSERDES2.
269 RST => '1' , -- 1-bit input: Reset to zero or 1/2 of total delay period
270 T => '1' -- 1-bit input: 3-state input signal
271 );
272
273 -- CMV_RESET <= not system_reset;
274 --TP2 <= FOO;
275 TP1 <= BAR ;
276
277 end Behavioral ;
von
Zac Zampo (Gast)
25.10.2012 15:16
C0 => "not"(LVDS_CLK), C1 => LVDS_CLK,
...
RST => '1', -- 1-bit input: Reset to zero or 1/2 of total
delay period
T => '1'
...
von
fred (Gast)
25.10.2012 15:25
Die aktuelle Version hat inzwischen nicht mehr den RESET auf 1:
1 library IEEE ;
2 use IEEE . STD_LOGIC_1164 . ALL ;
3 use IEEE . STD_LOGIC_UNSIGNED . ALL ;
4
5 library UNISIM ;
6 use UNISIM . VCOMPONENTS . ALL ;
7
8 entity delay_test is
9 port
10 (
11 REFCLK_PIN : in std_logic ;
12
13 FPGA_RESET : in std_logic ;
14
15 TP1 : out std_logic ;
16 TP2 : out std_logic
17 );
18 end delay_test ;
19
20 architecture Behavioral of delay_test is
21
22 -- DCMs
23 component dcm_master
24 port
25 (
26 CLKIN_IN : in std_logic ;
27 RST_IN : in std_logic ;
28 CLKFX000 : out std_logic
29 );
30 end component ;
31
32 component dcm_clock
33 port
34 (
35 CLKIN_IN : in std_logic ;
36 RST_IN : in std_logic ;
37 CLKDIV : out std_logic ;
38 CLK2X_OUT : out std_logic ;
39 CLKFX000 : out std_logic ;
40 LOCKED_OUT : out std_logic
41 );
42 end component ;
43
44 attribute IOB : string ;
45
46 -- Clocks
47 signal REFCLK : std_logic ;
48 signal PLL_CLK_FB , CMV_CLK_PLL : std_logic ;
49 signal LVDS_CLK_DCM , LVDS_CLK : std_logic ;
50
51 signal clk_32 : std_logic ;
52
53 signal system_reset : std_logic ;
54
55 signal FOO : std_logic ;
56
57 signal dcm_locked : std_logic ;
58
59 signal lvds_clk_iob : std_logic ;
60
61 signal LVDS_CLK_IODELAY_P , LVDS_CLK_IODELAY_N : std_logic ;
62 signal IODELAY_IO_RESET , IODELAY_CLK_RESET : std_logic ;
63 signal DELAY_DATA_CAL : std_logic ;
64
65 signal LVDS_CLK_P , LVDS_CLK_N : std_logic ;
66
67 signal LVDS_DATA_IN_BUF : std_logic ;
68
69 signal LVDS_CH1_IODELAY : std_logic ;
70
71 signal BAR : std_logic ;
72
73 signal I_CE , I_INC : std_logic ;
74
75 signal DOUT : std_logic ;
76
77 type VDELAY_FSM_STATES is (
78 STATUS_SET_CALC ,
79 STATUS_WAIT_CALC ,
80 STATUS_SET_RST ,
81 STATUS_WAIT_DELAY
82 );
83
84 --------------------------
85 -- TYPES
86 --------------------------
87 type FSM_STATUS is ( STATUS_SET_CAL ,
88 STATUS_WAIT_CAL ,
89 STATUS_SET_RST ,
90 STATUS_WAIT_DELAY
91 );
92
93
94 --------------------------
95 -- CONSTANTS
96 --------------------------
97 -- 1s delay
98 constant I_DELAY_MAX : integer : = 66666666 ;
99 constant I_DELAY_LED_MAX : integer : = 66666666 ;
100 -- 1ms delay
101 constant I_DELAY_DATA_MAX : integer : = 66666 ;
102
103 signal I_FSM_STATUS : FSM_STATUS ;
104
105 signal I_DATA : std_logic ;
106 signal I_DATA_DELAYED : std_logic ;
107
108 signal I_LED_OUT : std_logic ;
109
110 -- IODELAY CONTROL
111 signal I_IODELAY_CAL : std_logic ;
112 signal I_IODELAY_RST : std_logic ;
113 signal I_IODELAY_BUSY : std_logic ;
114
115 -- COUNTERS
116 signal I_CAL_DELAY : integer range 0 to I_DELAY_MAX ;
117 signal I_LED_DELAY : integer range 0 to I_DELAY_LED_MAX ;
118 signal I_DATA_DELAY : integer range 0 to I_DELAY_DATA_MAX ;
119
120 begin
121 system_reset <= not FPGA_RESET ;
122 REFCLK_BUFG_INST : BUFG port map ( I => REFCLK_PIN , O => REFCLK );
123
124 CMVCLK_INST : PLL_BASE
125 generic map
126 (
127 CLKIN_PERIOD => 20 . 000 ,
128 CLKFBOUT_MULT => 10 ,
129 CLK_FEEDBACK => "CLKFBOUT" ,
130 COMPENSATION => "SYSTEM_SYNCHRONOUS" ,
131
132 CLKOUT0_DIVIDE => 30 , -- MA Takt 100=5Mhz 50=10Mhz 25=20Mhz
133
134 CLKOUT0_PHASE => 0 . 000 ,
135 CLKOUT0_DUTY_CYCLE => 0 . 500
136 )
137 port map
138 (
139 CLKIN => REFCLK ,
140 RST => system_reset ,
141 CLKFBOUT => PLL_CLK_FB ,
142 CLKFBIN => PLL_CLK_FB ,
143
144 CLKOUT0 => CMV_CLK_PLL
145 );
146
147 -- -----------------------------------
148 --
149 -- LVDSCLK_DCM_INST: DCM_SP
150 -- generic map
151 -- (
152 -- CLKIN_PERIOD => 60.0, --50.0, --200.0, -- MA Takt 100=200 50=100 25=50
153 -- CLKFX_MULTIPLY => 10,
154 -- CLKFX_DIVIDE => 1,
155 -- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS"
156 -- )
157 -- port map
158 -- (
159 -- CLKIN => CMV_CLK_PLL,
160 -- RST => system_reset,
161 -- CLKFB => '0',
162 -- DSSEN => '0',
163 --
164 -- CLK0 => open,
165 -- CLKFX => LVDS_CLK_DCM,
166 --
167 -- LOCKED => dcm_locked
168 -- );
169 --
170 -- LVDSCLK_BUFG_INST: BUFG port map(I => LVDS_CLK_DCM, O => LVDS_CLK);
171 --
172 -- LVDS_CLK_ODDR2_INST: ODDR2
173 -- port map
174 -- (
175 -- C0 => "not"(LVDS_CLK), C1 => LVDS_CLK, -- FIXME: Phase 180° gedreht ??!!??
176 -- D0 => '1', D1 => '0',
177 -- CE => '1', R => '0', S => '0',
178 -- Q => LVDS_CLK_IOB
179 -- );
180 --
181 --
182 --
183 -- LVDS_CLK_IOB_INST: OBUFDS
184 -- generic map (IOSTANDARD => "LVDS_25")
185 -- port map (I => LVDS_CLK_IOB, O => LVDS_CLK_P, OB => LVDS_CLK_N);
186
187
188 cnt : process ( SYSTEM_RESET , REFCLK )
189 variable count : natural range 0 to 500000 ;
190 begin
191 if SYSTEM_RESET = '0' then
192 count : = 0 ;
193 TP2 <= '1' ;
194 elsif rising_edge ( REFCLK ) then
195 if count < 250000 then
196 count : = count + 1 ;
197 TP2 <= '1' ;
198 FOO <= '1' ;
199 elsif count < 500000 then
200 TP2 <= '0' ;
201 FOO <= '0' ;
202 count : = count + 1 ;
203 else
204 count : = 0 ;
205 end if ;
206 end if ;
207 end process cnt ;
208
209
210 cnt2 : process ( SYSTEM_RESET , REFCLK )
211 variable count : natural range 0 to 80000000 ;
212 begin
213 if SYSTEM_RESET = '0' then
214 count : = 0 ;
215 elsif rising_edge ( REFCLK ) then
216
217 if count = 40000000 then
218 I_INC <= '1' ;
219 I_CE <= '1' ;
220 end if ;
221
222 if count < 80000000 then
223 count : = count + 1 ;
224 else
225 count : = 0 ;
226 --I_CE <= '0';
227 --I_INC <= '0';
228 end if ;
229 end if ;
230 end process cnt2 ;
231
232 -- elsif count < 800000 then
233 -- I_CE <= '0';
234 -- I_INC <= '0';
235 -- count := count + 1;
236
237 UPDATE_CAL : process ( SYSTEM_RESET , REFCLK )
238 begin
239 if SYSTEM_RESET = '0' then
240 I_FSM_STATUS <= STATUS_SET_CAL ;
241 I_CAL_DELAY <= 0 ;
242 I_IODELAY_CAL <= '0' ;
243 I_IODELAY_RST <= '0' ;
244 elsif rising_edge ( REFCLK ) then
245
246 case I_FSM_STATUS is
247
248 when STATUS_SET_CAL =>
249 -- Set calibration for 1 clock
250 I_IODELAY_CAL <= '1' ;
251 I_FSM_STATUS <= STATUS_WAIT_CAL ;
252
253 when STATUS_WAIT_CAL =>
254 I_IODELAY_CAL <= '0' ;
255 I_FSM_STATUS <= STATUS_SET_RST ;
256
257 when STATUS_SET_RST =>
258 -- Wait busy signal
259 if I_IODELAY_BUSY = '0' then
260 -- Set reset signal
261 I_IODELAY_RST <= '1' ;
262 I_CAL_DELAY <= 0 ;
263 I_FSM_STATUS <= STATUS_WAIT_DELAY ;
264 end if ;
265
266 when STATUS_WAIT_DELAY =>
267 I_IODELAY_RST <= '0' ;
268 if I_CAL_DELAY = I_DELAY_MAX then
269 I_FSM_STATUS <= STATUS_SET_CAL ;
270 I_CAL_DELAY <= 0 ;
271 else
272 I_CAL_DELAY <= I_CAL_DELAY + 1 ;
273 end if ;
274
275 end case ;
276
277 end if ;
278
279 end process ;
280
281
282
283
284 IOBUF_NEU_INST : IOBUF
285 port map
286 (
287 I => FOO ,
288 O => LVDS_DATA_IN_BUF ,
289 T => '0' ,
290 IO => open
291 );
292
293 DA_INST : OBUF
294 port map
295 (
296 I => DOUT ,
297 O => BAR
298 );
299
300 IODELAY2_NEU_INST : IODELAY2
301 generic map (
302 COUNTER_WRAPAROUND => "WRAPAROUND" , -- "STAY_AT_LIMIT" or "WRAPAROUND"
303 DATA_RATE => "SDR" , -- "SDR" or "DDR"
304 DELAY_SRC => "IDATAIN" , -- "IO", "ODATAIN" or "IDATAIN"
305 IDELAY2_VALUE => 0 , -- Delay value when IDELAY_MODE="PCI" (0-255)
306 IDELAY_MODE => "NORMAL" , -- "NORMAL" or "PCI"
307 IDELAY_TYPE => "VARIABLE_FROM_ZERO" , -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
308 -- or "DIFF_PHASE_DETECTOR"
309 --IDELAY_VALUE => 255, -- Amount of taps for fixed input delay (0-255)
310 --ODELAY_VALUE => 255, -- Amount of taps fixed output delay (0-255)
311 SERDES_MODE => "NONE" , -- "NONE", "MASTER" or "SLAVE"
312 SIM_TAPDELAY_VALUE => 75 -- Per tap delay used for simulation in ps
313 )
314 port map (
315 BUSY => I_IODELAY_BUSY , -- 1-bit output: Busy output after CAL
316 DATAOUT => open , -- 1-bit output: Delayed data output to ISERDES/input register
317 DATAOUT2 => DOUT , -- 1-bit output: Delayed data output to general FPGA fabric
318 DOUT => open , -- 1-bit output: Delayed data output
319 TOUT => open , -- 1-bit output: Delayed 3-state output
320 CAL => I_IODELAY_CAL , -- 1-bit input: Initiate calibration input
321 CE => I_INC , -- 1-bit input: Enable INC input
322 CLK => CMV_CLK_PLL , -- 1-bit input: Clock input
323 IDATAIN => LVDS_DATA_IN_BUF , -- 1-bit input: Data input (connect to top-level port or I/O buffer)
324 INC => I_INC , --DELAY_DATA_INC, -- 1-bit input: Increment / decrement input
325 IOCLK0 => CMV_CLK_PLL , -- 1-bit input: Input from the I/O clock network
326 IOCLK1 => '0' , -- 1-bit input: Input from the I/O clock network
327 ODATAIN => '0' , -- 1-bit input: Output data input from output register or OSERDES2.
328 RST => I_IODELAY_RST , -- 1-bit input: Reset to zero or 1/2 of total delay period
329 T => '1' -- 1-bit input: 3-state input signal
330 );
331
332 -- CMV_RESET <= not system_reset;
333 --TP2 <= FOO;
334 --TP1 <= BAR;
335 TP1 <= BAR ;
336
337 end Behavioral ;
von
namenlos (Gast)
25.10.2012 15:29
mehrere Anmerkungen
1) nicht das Problem, aber Du solltest
a) numeric_std verwenden
b) KEINE asynchronen Resets
2)die DCM braucht wenigstens 3 Eingangs-Takte, um 100%ig zu
funktionieren
=> PLL-LOCKED -> inverter -> DCM-Reset
3)irgendwie stimmt Deine Reset-Polarität nicht:
entweder die PLL ist im Reset, oder Dein Counter !??
Viel Erfolg
von
Neuinbibi (Gast)
25.10.2012 16:14
Das kommt davon, wenn man negierte Signale ins Design reinschleppt.
Unnötige Fallen,
von
fred (Gast)
25.10.2012 16:21
Aktuelle Version: Synchrone Resets, PLL_LOCKED -> INVERTER -> DCM_RESET 1 library IEEE ;
2 --use IEEE.STD_LOGIC_1164.ALL;
3 --use IEEE.STD_LOGIC_UNSIGNED.ALL;
4 use IEEE . STD_LOGIC_1164 . ALL ;
5 use IEEE . NUMERIC_STD . ALL ;
6
7 library UNISIM ;
8 use UNISIM . VCOMPONENTS . ALL ;
9
10 entity delay_test is
11 port
12 (
13 REFCLK_PIN : in std_logic ;
14
15 FPGA_RESET : in std_logic ;
16
17 TP1 : out std_logic ;
18 TP2 : out std_logic
19 );
20 end delay_test ;
21
22 architecture Behavioral of delay_test is
23
24 -- DCMs
25 component dcm_master
26 port
27 (
28 CLKIN_IN : in std_logic ;
29 RST_IN : in std_logic ;
30 CLKFX000 : out std_logic
31 );
32 end component ;
33
34 component dcm_clock
35 port
36 (
37 CLKIN_IN : in std_logic ;
38 RST_IN : in std_logic ;
39 CLKDIV : out std_logic ;
40 CLK2X_OUT : out std_logic ;
41 CLKFX000 : out std_logic ;
42 LOCKED_OUT : out std_logic
43 );
44 end component ;
45
46 attribute IOB : string ;
47
48 -- Clocks
49 signal REFCLK : std_logic ;
50 signal PLL_CLK_FB , CMV_CLK_PLL : std_logic ;
51 signal LVDS_CLK_DCM , LVDS_CLK : std_logic ;
52
53 signal clk_32 : std_logic ;
54
55 signal system_reset : std_logic ;
56
57 signal FOO : std_logic ;
58
59 signal dcm_locked : std_logic ;
60
61 signal lvds_clk_iob : std_logic ;
62
63 signal LVDS_CLK_IODELAY_P , LVDS_CLK_IODELAY_N : std_logic ;
64 signal IODELAY_IO_RESET , IODELAY_CLK_RESET : std_logic ;
65 signal DELAY_DATA_CAL : std_logic ;
66
67 signal LVDS_CLK_P , LVDS_CLK_N : std_logic ;
68
69 signal LVDS_DATA_IN_BUF : std_logic ;
70
71 signal LVDS_CH1_IODELAY : std_logic ;
72
73 signal BAR : std_logic ;
74
75 signal I_CE , I_INC : std_logic ;
76
77 signal DOUT : std_logic ;
78
79 type VDELAY_FSM_STATES is (
80 STATUS_SET_CALC ,
81 STATUS_WAIT_CALC ,
82 STATUS_SET_RST ,
83 STATUS_WAIT_DELAY
84 );
85
86 --------------------------
87 -- TYPES
88 --------------------------
89 type FSM_STATUS is ( STATUS_SET_CAL ,
90 STATUS_WAIT_CAL ,
91 STATUS_SET_RST ,
92 STATUS_WAIT_DELAY
93 );
94
95
96 --------------------------
97 -- CONSTANTS
98 --------------------------
99 -- 1s delay
100 constant I_DELAY_MAX : integer : = 66666666 ;
101 constant I_DELAY_LED_MAX : integer : = 66666666 ;
102 -- 1ms delay
103 constant I_DELAY_DATA_MAX : integer : = 66666 ;
104
105 signal I_FSM_STATUS : FSM_STATUS ;
106
107 signal I_DATA : std_logic ;
108 signal I_DATA_DELAYED : std_logic ;
109
110 signal I_LED_OUT : std_logic ;
111
112 -- IODELAY CONTROL
113 signal I_IODELAY_CAL : std_logic ;
114 signal I_IODELAY_RST : std_logic ;
115 signal I_IODELAY_BUSY : std_logic ;
116
117 -- COUNTERS
118 signal I_CAL_DELAY : integer range 0 to I_DELAY_MAX ;
119 signal I_LED_DELAY : integer range 0 to I_DELAY_LED_MAX ;
120 signal I_DATA_DELAY : integer range 0 to I_DELAY_DATA_MAX ;
121
122 signal PLL_LOCKED : std_logic ;
123 signal DCM_RESET : std_logic ;
124
125 begin
126 --system_reset <= not FPGA_RESET;
127 REFCLK_BUFG_INST : BUFG port map ( I => REFCLK_PIN , O => REFCLK );
128
129 CMVCLK_INST : PLL_BASE
130 generic map
131 (
132 CLKIN_PERIOD => 20 . 000 ,
133 CLKFBOUT_MULT => 10 ,
134 CLK_FEEDBACK => "CLKFBOUT" ,
135 COMPENSATION => "SYSTEM_SYNCHRONOUS" ,
136
137 CLKOUT0_DIVIDE => 30 , -- MA Takt 100=5Mhz 50=10Mhz 25=20Mhz
138
139 CLKOUT0_PHASE => 0 . 000 ,
140 CLKOUT0_DUTY_CYCLE => 0 . 500
141 )
142 port map
143 (
144 CLKIN => REFCLK ,
145 RST => system_reset , -- FPGA_RESET is Active Low - SYSTEM_RESET ist FPGA_RESET invertiert!
146 CLKFBOUT => PLL_CLK_FB ,
147 CLKFBIN => PLL_CLK_FB ,
148
149 CLKOUT0 => CMV_CLK_PLL ,
150
151 LOCKED => PLL_LOCKED
152 );
153
154 -- -----------------------------------
155 --
156 LVDSCLK_DCM_INST : DCM_SP
157 generic map
158 (
159 CLKIN_PERIOD => 60 . 0 , --50.0, --200.0, -- MA Takt 100=200 50=100 25=50
160 CLKFX_MULTIPLY => 10 ,
161 CLKFX_DIVIDE => 1 ,
162 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS"
163 )
164 port map
165 (
166 CLKIN => CMV_CLK_PLL ,
167 RST => DCM_RESET , -- RESET auf HIGH solange die PLL nicht gelockt ist
168 CLKFB => '0' ,
169 DSSEN => '0' ,
170
171 CLK0 => open ,
172 CLKFX => LVDS_CLK_DCM ,
173
174 LOCKED => dcm_locked
175 );
176
177 LVDSCLK_BUFG_INST : BUFG port map ( I => LVDS_CLK_DCM , O => LVDS_CLK );
178 --
179 -- LVDS_CLK_ODDR2_INST: ODDR2
180 -- port map
181 -- (
182 -- C0 => "not"(LVDS_CLK), C1 => LVDS_CLK, -- FIXME: Phase 180° gedreht ??!!??
183 -- D0 => '1', D1 => '0',
184 -- CE => '1', R => '0', S => '0',
185 -- Q => LVDS_CLK_IOB
186 -- );
187 --
188 --
189 --
190 -- LVDS_CLK_IOB_INST: OBUFDS
191 -- generic map (IOSTANDARD => "LVDS_25")
192 -- port map (I => LVDS_CLK_IOB, O => LVDS_CLK_P, OB => LVDS_CLK_N);
193
194 --
195 --cnt : process(SYSTEM_RESET, REFCLK)
196 --variable count : natural range 0 to 500000;
197 --begin
198 -- if SYSTEM_RESET = '0' then
199 -- count := 0;
200 -- TP2 <= '1';
201 -- elsif rising_edge(REFCLK) then
202 -- if count < 250000 then
203 -- count := count + 1;
204 -- TP2 <= '1';
205 -- FOO <= '1';
206 -- elsif count < 500000 then
207 -- TP2 <= '0';
208 -- FOO <= '0';
209 -- count := count + 1;
210 -- else
211 -- count := 0;
212 -- end if;
213 -- end if;
214 --end process cnt;
215
216 -- NEU: Reset Synchron
217 cnt : process ( REFCLK )
218 variable count : natural range 0 to 500000 ;
219 begin
220 if ( refclk 'event and refclk = '1' ) then
221 if ( system_reset = '0' ) then
222 if count < 250000 then
223 count : = count + 1 ;
224 TP2 <= '1' ;
225 FOO <= '1' ;
226 elsif count < 500000 then
227 TP2 <= '0' ;
228 FOO <= '0' ;
229 count : = count + 1 ;
230 else
231 count : = 0 ;
232 end if ;
233 else
234 TP2 <= '0' ;
235 FOO <= '0' ;
236 end if ;
237 end if ;
238 end process cnt ;
239
240 --cnt2 : process(SYSTEM_RESET, REFCLK)
241 --variable count : natural range 0 to 80000000;
242 --begin
243 -- if SYSTEM_RESET = '0' then
244 -- count := 0;
245 -- elsif rising_edge(REFCLK) then
246 --
247 -- if count = 40000000 then
248 -- I_INC <= '1';
249 -- I_CE <= '1';
250 -- end if;
251 --
252 -- if count < 80000000 then
253 -- count := count + 1;
254 -- else
255 -- count := 0;
256 -- --I_CE <= '0';
257 -- --I_INC <= '0';
258 -- end if;
259 -- end if;
260 --end process cnt2;
261
262 cnt2 : process ( REFCLK )
263 variable count : natural range 0 to 80000000 ;
264 begin
265 if ( refclk 'event and refclk = '1' ) then
266 if ( system_reset = '0' ) then
267
268 if count = 40000000 then
269 I_INC <= '1' ;
270 I_CE <= '1' ;
271 end if ;
272
273 if count < 80000000 then
274 count : = count + 1 ;
275 else
276 count : = 0 ;
277 I_CE <= '0' ;
278 I_INC <= '0' ;
279 end if ;
280 else
281 I_CE <= '0' ;
282 I_INC <= '0' ;
283 end if ;
284 end if ;
285 end process cnt2 ;
286
287 -- elsif count < 800000 then
288 -- I_CE <= '0';
289 -- I_INC <= '0';
290 -- count := count + 1;
291
292 --UPDATE_CAL : process(SYSTEM_RESET, REFCLK)
293 --begin
294 -- if SYSTEM_RESET = '0' then
295 -- I_FSM_STATUS <= STATUS_SET_CAL;
296 -- I_CAL_DELAY <= 0;
297 -- I_IODELAY_CAL <= '0';
298 -- I_IODELAY_RST <= '0';
299 -- elsif rising_edge(REFCLK) then
300 --
301 -- case I_FSM_STATUS is
302 --
303 -- when STATUS_SET_CAL =>
304 -- -- Set calibration for 1 clock
305 -- I_IODELAY_CAL <= '1';
306 -- I_FSM_STATUS <= STATUS_WAIT_CAL;
307 --
308 -- when STATUS_WAIT_CAL =>
309 -- I_IODELAY_CAL <= '0';
310 -- I_FSM_STATUS <= STATUS_SET_RST;
311 --
312 -- when STATUS_SET_RST =>
313 -- -- Wait busy signal
314 -- if I_IODELAY_BUSY = '0' then
315 -- -- Set reset signal
316 -- I_IODELAY_RST <= '1';
317 -- I_CAL_DELAY <= 0;
318 -- I_FSM_STATUS <= STATUS_WAIT_DELAY;
319 -- end if;
320 --
321 -- when STATUS_WAIT_DELAY =>
322 -- I_IODELAY_RST <= '0';
323 -- if I_CAL_DELAY = I_DELAY_MAX then
324 -- I_FSM_STATUS <= STATUS_SET_CAL;
325 -- I_CAL_DELAY <= 0;
326 -- else
327 -- I_CAL_DELAY <= I_CAL_DELAY+1;
328 -- end if;
329 --
330 -- end case;
331
332 update_cal : process ( refclk )
333 begin
334 if ( refclk 'event and refclk = '1' ) then
335 if ( system_reset = '0' ) then
336
337 case I_FSM_STATUS is
338
339 when STATUS_SET_CAL =>
340 -- Set calibration for 1 clock
341 I_IODELAY_CAL <= '1' ;
342 I_FSM_STATUS <= STATUS_WAIT_CAL ;
343
344 when STATUS_WAIT_CAL =>
345 I_IODELAY_CAL <= '0' ;
346 I_FSM_STATUS <= STATUS_SET_RST ;
347
348 when STATUS_SET_RST =>
349 -- Wait busy signal
350 if I_IODELAY_BUSY = '0' then
351 -- Set reset signal
352 I_IODELAY_RST <= '1' ;
353 I_CAL_DELAY <= 0 ;
354 I_FSM_STATUS <= STATUS_WAIT_DELAY ;
355 end if ;
356
357 when STATUS_WAIT_DELAY =>
358 I_IODELAY_RST <= '0' ;
359 if I_CAL_DELAY = I_DELAY_MAX then
360 I_FSM_STATUS <= STATUS_SET_CAL ;
361 I_CAL_DELAY <= 0 ;
362 else
363 I_CAL_DELAY <= I_CAL_DELAY + 1 ;
364 end if ;
365 end case ;
366
367 else
368 I_FSM_STATUS <= STATUS_SET_CAL ;
369 I_CAL_DELAY <= 0 ;
370 I_IODELAY_CAL <= '0' ;
371 I_IODELAY_RST <= '0' ;
372 end if ;
373 end if ;
374 end process ;
375
376
377
378
379 IOBUF_NEU_INST : IOBUF
380 port map
381 (
382 I => FOO ,
383 O => LVDS_DATA_IN_BUF ,
384 T => '0' ,
385 IO => open
386 );
387
388 DA_INST : OBUF
389 port map
390 (
391 I => DOUT ,
392 O => BAR
393 );
394
395 IODELAY2_NEU_INST : IODELAY2
396 generic map (
397 COUNTER_WRAPAROUND => "WRAPAROUND" , -- "STAY_AT_LIMIT" or "WRAPAROUND"
398 DATA_RATE => "SDR" , -- "SDR" or "DDR"
399 DELAY_SRC => "IDATAIN" , -- "IO", "ODATAIN" or "IDATAIN"
400 IDELAY2_VALUE => 0 , -- Delay value when IDELAY_MODE="PCI" (0-255)
401 IDELAY_MODE => "NORMAL" , -- "NORMAL" or "PCI"
402 IDELAY_TYPE => "VARIABLE_FROM_ZERO" , -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
403 -- or "DIFF_PHASE_DETECTOR"
404 --IDELAY_VALUE => 255, -- Amount of taps for fixed input delay (0-255)
405 --ODELAY_VALUE => 255, -- Amount of taps fixed output delay (0-255)
406 SERDES_MODE => "NONE" , -- "NONE", "MASTER" or "SLAVE"
407 SIM_TAPDELAY_VALUE => 75 -- Per tap delay used for simulation in ps
408 )
409 port map (
410 BUSY => I_IODELAY_BUSY , -- 1-bit output: Busy output after CAL
411 DATAOUT => open , -- 1-bit output: Delayed data output to ISERDES/input register
412 DATAOUT2 => DOUT , -- 1-bit output: Delayed data output to general FPGA fabric
413 DOUT => open , -- 1-bit output: Delayed data output
414 TOUT => open , -- 1-bit output: Delayed 3-state output
415 CAL => I_IODELAY_CAL , -- 1-bit input: Initiate calibration input
416 CE => I_CE , -- 1-bit input: Enable INC input
417 CLK => LVDS_CLK , -- 1-bit input: Clock input
418 IDATAIN => LVDS_DATA_IN_BUF , -- 1-bit input: Data input (connect to top-level port or I/O buffer)
419 INC => I_INC , --DELAY_DATA_INC, -- 1-bit input: Increment / decrement input
420 IOCLK0 => LVDS_CLK , -- 1-bit input: Input from the I/O clock network
421 IOCLK1 => '0' , -- 1-bit input: Input from the I/O clock network
422 ODATAIN => '0' , -- 1-bit input: Output data input from output register or OSERDES2.
423 RST => I_IODELAY_RST , -- 1-bit input: Reset to zero or 1/2 of total delay period
424 T => '1' -- 1-bit input: 3-state input signal
425 );
426
427 RESET_INV_INST : INV
428 port map (
429 I => FPGA_RESET ,
430 O => SYSTEM_RESET
431 );
432
433 DCM_LOCKED_INV_INST : INV
434 port map (
435 I => PLL_LOCKED ,
436 O => DCM_RESET
437 );
438
439
440 -- CMV_RESET <= not system_reset;
441 --TP2 <= FOO;
442 --TP1 <= BAR;
443 TP1 <= BAR ;
444
445 end Behavioral ;
von
namenlos (Gast)
25.10.2012 16:47
und nu?
WAS geht nicht -> die Hardware, oder die Simulation?
von
fred (Gast)
25.10.2012 16:57
@namenlos:
Die Hardware. Ich gebe die beiden Signale (Nicht verzögert und verzögert
auf zwei Test-Pads) aus und gucke sie mir an. Das verzögerte Signal
verschiebt sich aber um kein Stück.
von
namenlos (Gast)
25.10.2012 17:04
fast selbsterklärend:
es steht also eine (funktionale) Simulation an - in der ISE in 2 min.
aufgesetzt, da in Deinem mini-Design fast alles automatisiert generiert
wird
- nur die Clock und der Reset müssen stimuliert werden
clock <= not clock after clock_period/2;
reset_n <= '1' after startup_delay;
Dann im wave-viewer die Signale ansehen und...
alles andere ist nur Kaffeesatzleserei
von
namenlos (Gast)
25.10.2012 17:21
Nachtrag:
hab' jetzt nochmal kurz in den Code reingeschaut:
- "rising_edge(clock)" war schöner als Deine jetzige Beschreibung
- ungewöhnliche Beschreibung eines sync resets (geht zwar, aber
ungewöhnlich)
besser:
if rising_edge(clk) then
if (reset = '1') then
elsif (clock_enable = '1') then
end if;
end if;
- Instantiierungen vermeiden, wo immer möglich.
also
reset <= not locked;
- ISIM unterstützt keine Variablen-Ansicht
-> verwende für deine beiden Counter Signale; sonst kannst Du nicht
im wave-viewer vernünftig debuggen!
von
fred (Gast)
25.10.2012 20:04
Hab ich bereits geändert. Im Testbench passiert nichts - an TP1 und TP2
ist kein Signal zu sehen. Auf der Hardware jedoch 2 identische Signale.
von
fred (Gast)
26.10.2012 11:38
Bin leider immernoch nicht weitergekommen. Der Testbench läuft nicht
korrekt (TP1 und TP2 ändern die States nicht) und auf der Hardware ist
das Signal auch nicht verzögert.
von
namenlos (Gast)
26.10.2012 13:04
und was sagen dir "internen" Signale in der Testbench?
Muss ja einen Grund haben, warum sich nichts tut - zum vereinfachten
Simulieren evtl. die Counter nicht so 'weit' zählen lassen; es geht ja
nur um die prinzipielle Funktionsfähigkeit.
In der Hardware zu debuggen wäre prinzipiell möglich (mit ChupScope wenn
man eine Lizenz hat), da man dort aber nicht ins IDELAY 'reinsehen kann,
etwas schwieriger..
Prinzipiell kann ich nur sagen, DASS es funktioniert: hab' es schon
gemacht - aber nur in der 'alten' Firma, so dass ich aktuell keine
Sourcen vorliegen habe...
Viel Erfolg
Anbei das vhdl mit den essentieller Typographieanpassungen.
Folgendenes Schnipsel solltest du nochmal durchdenken:
1 variable count : natural range 0 to 500000 ; --!
2 begin
3 if ( refclk 'event and refclk = '1' ) then
4 if system_reset = '0' then
5 if count < 250000 then --!
6 count : = count + 1 ;
7
8 elsif count < 500000 then --!
9
10 count : = count + 1 ;
11 else --!
12 count : = 0 ;
13 end if ;
14 else
15 TP2 <= '0' ;
16 FOO <= '0' ;
17 end if ;
18 end if ;
19 end process cnt ;
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