Hi all,
I have sucessfully checked the initialisationand transmit operations of
my CAN opencore (Linux PC --- > Laptop+CAN Analyser) with the following
code:
---------MemoryMap CAN = 0x3000 -----------------------
#define CAN_CONTROL_REG 0x00
#define CAN_COMMAND_REG 0x01
#define CAN_STATUS_REG 0x02
#define CAN_INTERRUPT_REG 0x03
#define CAN_ACCEPTANCE_CODE 0x04
#define CAN_ACCEPTANCE_MASK 0x05
#define CAN_BUSTIMING_0 0x06
#define CAN_BUSTIMING_1 0x07
#define CAN_TX_IDENT_0 0x0A
#define CAN_TX_IDENT_1 0x0B
#define CAN_TX_DATA_1 0x0C
#define CAN_TX_DATA_2 0x0D
#define CAN_TX_DATA_3 0x0E
#define CAN_TX_DATA_4 0x0F
#define CAN_TX_DATA_5 0x10
#define CAN_TX_DATA_6 0x11
#define CAN_TX_DATA_7 0x12
#define CAN_TX_DATA_8 0x13
#define CAN_RX_IDENT_0 0x14
#define CAN_RX_IDENT_1 0x15
#define CAN_RX_DATA_1 0x16
#define CAN_RX_DATA_2 0x17
#define CAN_RX_DATA_3 0x18
#define CAN_RX_DATA_4 0x19
#define CAN_RX_DATA_5 0x1A
#define CAN_RX_DATA_6 0x1B
#define CAN_RX_DATA_7 0x1C
#define CAN_RX_DATA_8 0x1D
#define CAN_CLK_DIVIDER 0x1F
.......
#
# Can Initialisation from Linux PC
#
#
./regWr 0x3000 b 0x1F
./regWr 0x3004 b 0x72
./regWr 0x3005 b 0x58
./regWr 0x3006 b 0x00
./regWr 0x3007 b 0x7F
./regWr 0x301F b 0x05
./regWr 0x3000 b 0x1E
./regWr 0x3003 b 0x04
./regWr 0x3002 b 0x04
#
#
# Cand Send Message from Linux PC
#
#
./regWr 0x300A b 0x08
./regWr 0x300B b 0x48
./regWr 0x300C b 0x09
./regWr 0x300D b 0x09
./regWr 0x300E b 0x08
./regWr 0x300F b 0x08
./regWr 0x3010 b 0x07
./regWr 0x3011 b 0x07
./regWr 0x3012 b 0x06
./regWr 0x3013 b 0x06
./regWr 0x3001 b 0x01
Now my concern is to send a CAN Msg from CAN Analyser and see this on my
Linux PC. what should I do ?
The first thing I noticed is there is no Rcv Registers (Then I though
maybe it uses the same Tx by receiving)
So
1) am I rigth by considering that: Rx registers = Tx registers ? which
registers should I check for a Message send from the CAN Analyser ?
2) In which sequencies should I set those registers in order to activate
the receiving operation ?
within the CAN_REGISTERS Files there is no mentions about Receive
registers
/* This section is for BASIC and EXTENDED mode */
wire we_acceptance_code_0 = cs & we & reset_mode &
((~extended_mode) & (addr == 8'd4) | extended_mode & (addr == 8'd16));
wire we_acceptance_mask_0 = cs & we & reset_mode &
((~extended_mode) & (addr == 8'd5) | extended_mode & (addr == 8'd20));
wire we_tx_data_0 = cs & we & (~reset_mode) &
((~extended_mode) & (addr == 8'd10) | extended_mode & (addr == 8'd16)) &
transmit_buffer_status;
wire we_tx_data_1 = cs & we & (~reset_mode) &
((~extended_mode) & (addr == 8'd11) | extended_mode & (addr == 8'd17)) &
transmit_buffer_status;
wire we_tx_data_2 = cs & we & (~reset_mode) &
((~extended_mode) & (addr == 8'd12) | extended_mode & (addr == 8'd18)) &
transmit_buffer_status;
wire we_tx_data_3 = cs & we & (~reset_mode) &
((~extended_mode) & (addr == 8'd13) | extended_mode & (addr == 8'd19)) &
transmit_buffer_status;
wire we_tx_data_4 = cs & we & (~reset_mode) &
((~extended_mode) & (addr == 8'd14) | extended_mode & (addr == 8'd20)) &
transmit_buffer_status;
wire we_tx_data_5 = cs & we & (~reset_mode) &
((~extended_mode) & (addr == 8'd15) | extended_mode & (addr == 8'd21)) &
transmit_buffer_status;
wire we_tx_data_6 = cs & we & (~reset_mode) &
((~extended_mode) & (addr == 8'd16) | extended_mode & (addr == 8'd22)) &
transmit_buffer_status;
wire we_tx_data_7 = cs & we & (~reset_mode) &
((~extended_mode) & (addr == 8'd17) | extended_mode & (addr == 8'd23)) &
transmit_buffer_status;
wire we_tx_data_8 = cs & we & (~reset_mode) &
((~extended_mode) & (addr == 8'd18) | extended_mode & (addr == 8'd24)) &
transmit_buffer_status;
wire we_tx_data_9 = cs & we & (~reset_mode) &
((~extended_mode) & (addr == 8'd19) | extended_mode & (addr == 8'd25)) &
transmit_buffer_status;
So I would appreciate any advice allowing me to move forward.
