Endlosschleife für Konstante, nicht aber für direkten Wert

entity s is

  port

  (

    a: in std_logic;

    b: out std_logic

  );

end s;

architecture v1 of s is

begin

  b <= not a;

end v1;

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity testbench IS

END testbench;

architecture v1 of testbench is

  component s

    port

    (

      a: in std_logic;

      b: out std_logic;

    );

  end component;

  signal a: std_logic := '0';

  signal b: std_logic := '0';

  --constants not working?

  constant ct: time := 1 ms;

begin

  a <= not a after ct;

  dut: s

    port map

    (

      a => a,

      b => b,

    );

end architecture;