| 1 | /* main.c: performs a single transfer from DSPI_C to DSPI_D on MPC555x*/
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| 2 | /* Rev 1.0 Sept 14 2004 S.Mihalik */
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| 3 | /* Rev 2.0 Jan 3 2007 S. Mihalik - Modified to use two SPIs */
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| 4 | /* Rev 2.1 July 20 2007 SM - Modified for MPC551x, changed sysclk (50 MHz) */
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| 5 | /* Rev 2.2 Aug 13 2007 SM - Modified for sysclk of 64 MHz & lenghened CSSCK, ASC*/
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| 6 | /* Rev 2.3 Jun 04 2008 SM - initSysclk changed for MPC5633M support */
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| 7 | /* Rev 2.4 Aug 15 2008 SM - removed lines for MPC551x, MPC563x */
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| 8 | /* Rev 2.5 Aug 18 2008 D McKenna- Kept DSPI_MCR[HALT] set during initialization*/
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| 9 | /* Copyright Freescale Semiconductor, Inc. 2007 All rights reserved. */
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| 10 | /* Notes: */
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| 11 | /* 1. MMU not initialized; must be done by debug scripts or BAM */
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| 12 | /* 2. SRAM not initialized; must be done by debug scripts or in a crt0 type file */
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| 13 | 
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| 14 | #include "mpc5554.h" /* Use proper include file like mpc5510.h or mpc5554.h */
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| 15 | 
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| 16 | vuint32_t i = 0; /* Dummy idle counter */
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| 17 | uint16_t RecDataMaster = 0; /* Data recieved on master SPI */
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| 18 | uint16_t RecDataSlave = 0; /* Data received on slave SPI */
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| 19 | 
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| 20 | void initSysclk (void) {
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| 21 |   FMPLL.SYNCR.R = 0x16080000; /* 8 MHz xtal: 0x16080000; 40MHz: 0x46100000 */
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| 22 |   while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */
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| 23 |   FMPLL.SYNCR.R = 0x16000000; /* 8 MHz xtal: 0x16000000; 40MHz: 0x46080000 */
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| 24 | }
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| 25 | 
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| 26 | void initDSPI_C(void) {
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| 27 |   DSPI_C.MCR.R = 0x80010001; /* Configure DSPI_C as master */
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| 28 |   DSPI_C.CTAR[0].R = 0x780A7727; /* Configure CTAR0 */
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| 29 |   DSPI_C.MCR.B.HALT = 0x0; /* Exit HALT mode: go from STOPPED to RUNNING state*/
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| 30 |   SIU.PCR[107].R = 0x0A00; /* MPC555x: Config pad as DSPI_C SOUT output */
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| 31 |   SIU.PCR[108].R = 0x0900; /* MPC555x: Config pad as DSPI_C SIN input */
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| 32 |   SIU.PCR[109].R = 0x0A00; /* MPC555x: Config pad as DSPI_C SCK output */
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| 33 |   SIU.PCR[110].R = 0x0A00; /* MPC555x: Config pad as DSPI_C PCS0 output */
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| 34 | }
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| 35 | 
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| 36 | void initDSPI_D(void) {
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| 37 |   DSPI_D.MCR.R = 0x00010001; /* Configure DSPI_D as slave */
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| 38 |   DSPI_D.CTAR[0].R = 0x780A7727; /* Configure CTAR0 */
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| 39 |   DSPI_D.MCR.B.HALT = 0x0; /* Exit HALT mode: go from STOPPED to RUNNING state*/
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| 40 |   SIU.PCR[98].R = 0x0900; /* MPC555x: Config pad as DSPI_D SCK input */
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| 41 |   SIU.PCR[99].R = 0x0900; /* MPC555x: Config pad as DSPI_D SIN input */
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| 42 |   SIU.PCR[100].R = 0x0A00; /* MPC555x: Config pad as DSPI_D SOUT output*/
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| 43 |   SIU.PCR[106].R = 0x0900; /* MPC555x: Config pad as DSPI_D PCS0/SS input */
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| 44 | }
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| 45 | 
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| 46 | void ReadDataDSPI_D(void) {
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| 47 |   while (DSPI_D.SR.B.RFDF != 1){} /* Wait for Receive FIFO Drain Flag = 1 */
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| 48 |   RecDataSlave = DSPI_D.POPR.R; /* Read data received by slave SPI */
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| 49 |   DSPI_D.SR.R = 0x80020000; /* Clear TCF, RDRF flags by writing 1 to them */
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| 50 | }
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| 51 | 
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| 52 | void ReadDataDSPI_C(void) {
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| 53 |   while (DSPI_C.SR.B.RFDF != 1){} /* Wait for Receive FIFO Drain Flag = 1 */
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| 54 |   RecDataMaster = DSPI_C.POPR.R; /* Read data received by master SPI */
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| 55 |   DSPI_C.SR.R = 0x90020000; /* Clear TCF, RDRF, EOQ flags by writing 1 */
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| 56 | }
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| 57 | 
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| 58 | int main(void) {
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| 59 |   SIU.DISR.R = 0x0000C0FC; /* MPC555x only: Connect DSPI_C, DSPI_D internally */
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| 60 |   initSysclk(); /* Set sysclk = 64MHz running from PLL */
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| 61 |   initDSPI_C(); /* Initialize DSPI_C as master SPI and init CTAR0 */
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| 62 |   initDSPI_D(); /* Initialize DSPI_D as Slave SPI and init CTAR0 */
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| 63 |   DSPI_D.PUSHR.R = 0x00001234; /* Initialize slave DSPI_D's response to master */
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| 64 |   DSPI_C.PUSHR.R = 0x08015678; /* Transmit data from master to slave SPI with EOQ */
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| 65 |   ReadDataDSPI_D(); /* Read data on slave DSPI */
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| 66 |   ReadDataDSPI_C(); /* Read data on master DSPI */
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| 67 |   while (1) {i++; } /* Wait forever */
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| 68 | }
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