TIM-Example STM32F4 Discovery example

[Olli (Gast)]

Hallo Leute,

versuche mich gerade an dem Timer- und PWM-Beispiel.
Ich verstehe aber die 2. Rechnung in dem Beispiel nicht.
Dort steht ja folgendes:

  /* 
-----------------------------------------------------------------------
    TIM3 Configuration: generate 4 PWM signals with 4 different duty 
cycles.

    In this example TIM3 input clock (TIM3CLK) is set to 2 * APB1 clock 
(PCLK1),
    since APB1 prescaler is different from 1.
      TIM3CLK = 2 * PCLK1
      PCLK1 = HCLK / 4
      => TIM3CLK = HCLK / 2 = SystemCoreClock /2

    To get TIM3 counter clock at 28 MHz, the prescaler is computed as 
follows:
       Prescaler = (TIM3CLK / TIM3 counter clock) - 1
       Prescaler = ((SystemCoreClock /2) /28 MHz) - 1

    To get TIM3 output clock at 30 KHz, the period (ARR)) is computed as 
follows:
       ARR = (TIM3 counter clock / TIM3 output clock) - 1
           = 665

    TIM3 Channel1 duty cycle = (TIM3_CCR1/ TIM3_ARR)* 100 = 50%
    TIM3 Channel2 duty cycle = (TIM3_CCR2/ TIM3_ARR)* 100 = 37.5%
    TIM3 Channel3 duty cycle = (TIM3_CCR3/ TIM3_ARR)* 100 = 25%
    TIM3 Channel4 duty cycle = (TIM3_CCR4/ TIM3_ARR)* 100 = 12.5%

    Note:
     SystemCoreClock variable holds HCLK frequency and is defined in 
system_stm32f4xx.c file.
     Each time the core clock (HCLK) changes, user had to call 
SystemCoreClockUpdate()
     function to update SystemCoreClock variable value. Otherwise, any 
configuration
     based on this variable will be incorrect.
  ----------------------------------------------------------------------- 
*/

Der Prescaler erzeugt doch einen 28MHz-Takt.
Wenn ich aber nun auf 30kHz kommen möchte, dann komme ich mit
der Rechnung ARR = (TIM3 counter clock / TIM3 output clock) - 1, also
                    28Mhz / 30 kHz auf 932, nicht auf 665.
Ist das ein Fehler im Beispiel oder verstehe ich etwas nicht richtig.

LG Olli

[Uwe B. (derexponent)]

ist ein Fehler in der Doku, deine Rechnung ist richtig

in der neuen Version haben sie das Beispiel und den Text geändert :

  /* -----------------------------------------------------------------------
    TIM3 Configuration: generate 4 PWM signals with 4 different duty cycles.
    
    In this example TIM3 input clock (TIM3CLK) is set to 2 * APB1 clock (PCLK1), 
    since APB1 prescaler is different from 1.   
      TIM3CLK = 2 * PCLK1  
      PCLK1 = HCLK / 4 
      => TIM3CLK = HCLK / 2 = SystemCoreClock /2
          
    To get TIM3 counter clock at 21 MHz, the prescaler is computed as follows:
       Prescaler = (TIM3CLK / TIM3 counter clock) - 1
       Prescaler = ((SystemCoreClock /2) /21 MHz) - 1
                                              
    To get TIM3 output clock at 30 KHz, the period (ARR)) is computed as follows:
       ARR = (TIM3 counter clock / TIM3 output clock) - 1
           = 665
                  
    TIM3 Channel1 duty cycle = (TIM3_CCR1/ TIM3_ARR)* 100 = 50%
    TIM3 Channel2 duty cycle = (TIM3_CCR2/ TIM3_ARR)* 100 = 37.5%
    TIM3 Channel3 duty cycle = (TIM3_CCR3/ TIM3_ARR)* 100 = 25%
    TIM3 Channel4 duty cycle = (TIM3_CCR4/ TIM3_ARR)* 100 = 12.5%

    Note: 
     SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f4xx.c file.
     Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate()
     function to update SystemCoreClock variable value. Otherwise, any configuration
     based on this variable will be incorrect.    
  ----------------------------------------------------------------------- */

wobei hier die Werte auch nicht ganz stimmen
es sind nicht "genau" 30kHz sondern 31,53kHz

in der Readme steht die Rechnung nochmal mit den richtigen Zahlen

The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), to get TIM3 counter
clock at 21 MHz the Prescaler is computed as following:
   - Prescaler = (TIM3CLK / TIM3 counter clock) - 1

SystemCoreClock is set to 168 MHz for STM32F4xx Devices.

The TIM3 is running at 30 KHz: TIM3 Frequency = TIM3 counter clock/(ARR + 1)
                                              = 21 MHz / 666 = 31.530 KHz
The TIM3 CCR1 register value is equal to 333, so the TIM3 Channel 1 generates a 
PWM signal with a frequency equal to 30 KHz and a duty cycle equal to 50%:
TIM3 Channel1 duty cycle = (TIM3_CCR1/ TIM3_ARR + 1)* 100 = 50%

[Olli (Gast)]

Dankeschön