Lattice ECP3 Serdes

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity top is

end top;

architecture behaviour of top is

  signal Reset       : std_logic := '1'; -- LVDS clock output pair

  signal Reset_n       : std_logic; -- LVDS clock output pair

  signal CLK_Tx       : std_logic := '0'; -- LVDS clock output pair

  signal refclkp       : std_logic := '0'; -- LVDS clock output pair

  signal refclkn      : std_logic := '1'; -- LVDS clock output pair

  signal data_in     : std_logic_vector(15 downto 0) := "0000010000000000";

  signal data_out_p  : std_logic := '0';

  signal data_out_n  : std_logic := '0';

  signal tx_half_clk_ch0  : std_logic;

  signal tx_full_clk_ch0  : std_logic;

  signal tx_pll_lol_qd_s  : std_logic;

  signal refclk2fpga  : std_logic;

  component PCS0

  GENERIC (

    USER_CONFIG_FILE    :  String := "PCS0.txt");

  port (

    -- CH0 --

    hdoutp_ch0      :   out std_logic;

    hdoutn_ch0      :   out std_logic;

    txiclk_ch0      :   in std_logic;

    tx_full_clk_ch0    :   out std_logic;

    tx_half_clk_ch0    :   out std_logic;

    txdata_ch0      :   in std_logic_vector (15 downto 0);

    tx_k_ch0      :   in std_logic_vector (1 downto 0);

    tx_force_disp_ch0  :   in std_logic_vector (1 downto 0);

    tx_disp_sel_ch0    :   in std_logic_vector (1 downto 0);

    tx_pwrup_ch0_c    :   in std_logic;

    tx_div2_mode_ch0_c  : in std_logic;

    ---- Miscillaneous ports

    fpga_txrefclk  :   in std_logic;

    tx_serdes_rst_c  :   in std_logic;

    tx_pll_lol_qd_s  :   out std_logic;

    refclk2fpga    :   out std_logic;

    rst_n      :   in std_logic;

    serdes_rst_qd_c  :   in std_logic

  );

  end component;

begin

  Reset_n <= not Reset;

  PCS0_inst: PCS0

    port map(

      -- CH0 --

      hdoutp_ch0 => data_out_p,

      hdoutn_ch0 => data_out_n,

      txiclk_ch0 => CLK_Tx,

      tx_full_clk_ch0 => tx_full_clk_ch0,

      tx_half_clk_ch0 => tx_half_clk_ch0,

      txdata_ch0 => data_in,

      tx_k_ch0 => "11",

      tx_force_disp_ch0 => "00",

      tx_disp_sel_ch0 => "00",

      tx_pwrup_ch0_c => '1',

      tx_div2_mode_ch0_c => '0',

      ---- Miscillaneous ports

      fpga_txrefclk => CLK_Tx,

      tx_serdes_rst_c => Reset,

      tx_pll_lol_qd_s => tx_pll_lol_qd_s,

      refclk2fpga => refclk2fpga,

      rst_n => Reset_n,

      serdes_rst_qd_c => Reset

    );

process

begin

  wait for 4ns;

  CLK_Tx <= not CLK_Tx;

end process;     

process

begin

  wait for 5ns;

  Reset <= '0';

end process;     

end behaviour;