Hallo, guten Tag.
Ich bekomme es nicht hin, RS_Data in das speicher_ram zu packen.
Ich habe meine VHDL wieder verworfen, weil es keinen richtigen Anfang
gibt.
Wer kann da mal helfen?
Die RS232-Empfangsroutine funktioniert im Test weil die LED so blinken
wie die Daten vorhanden sind.
Danke.
Gruss
1 | library IEEE;
|
2 | use IEEE.STD_LOGIC_1164.ALL;
|
3 | use IEEE.NUMERIC_STD.ALL;
|
4 |
|
5 | entity ram_array is
|
6 | Generic ( Quarz_Taktfrequenz : integer := 50000000;
|
7 | Baudrate : integer := 9600
|
8 | );
|
9 | port(
|
10 | clk : in std_logic;
|
11 | RXD : in STD_LOGIC;
|
12 | );
|
13 | end ram_array;
|
14 |
|
15 | architecture Behavioral of ram_array is
|
16 |
|
17 | signal rxd_sr : std_logic_vector (3 downto 0) := "1111";
|
18 | signal rxsr : std_logic_vector (7 downto 0) := "00000000";
|
19 | signal rxbitcnt : integer range 0 to 9 := 9;
|
20 | signal rxcnt : integer range 0 to (Quarz_Taktfrequenz/Baudrate)-1;
|
21 | signal RX_Data : STD_LOGIC_VECTOR (7 downto 0);
|
22 | signal RX_Busy : STD_LOGIC;
|
23 |
|
24 | Type Ram128x8 is ARRAY (0 to 127) OF unsigned(7 downto 0);
|
25 | signal speicher_ram : Ram128x8;
|
26 |
|
27 | signal RamAddr: integer range 0 to 127 := 0;
|
28 |
|
29 | begin
|
30 |
|
31 | process(clk)
|
32 | begin
|
33 | .................
|
34 | .................
|
35 | end process;
|
36 |
|
37 | process(clk)
|
38 | begin
|
39 | if rising_edge(clk) then
|
40 | rxd_sr <= rxd_sr(rxd_sr'left-1 downto 0) & RXD;
|
41 | if (rxbitcnt<9) then
|
42 | if(rxcnt<(Quarz_Taktfrequenz/Baudrate)-1) then
|
43 | rxcnt <= rxcnt+1;
|
44 | else
|
45 | rxcnt <= 0;
|
46 | rxbitcnt <= rxbitcnt+1;
|
47 | rxsr <= rxd_sr(rxd_sr'left-1) & rxsr(rxsr'left downto 1);
|
48 | end if;
|
49 | else
|
50 | if (rxd_sr(3 downto 2) = "10") then
|
51 | rxcnt <= ((Quarz_Taktfrequenz/Baudrate)-1)/2;
|
52 | rxbitcnt <= 0;
|
53 | end if;
|
54 | end if;
|
55 | end if;
|
56 | end process;
|
57 |
|
58 | RX_Data <= rxsr;
|
59 | RX_Busy <= '1' when (rxbitcnt<9) else '0';
|
60 | end Behavioral;
|
