UART mit XMC2GO

//////////////////////////////////////////////////////

//

// Diese Quellcodedatei wurde automatisch erzeugt.

// SiSy UML CodeGenerierung

//

//////////////////////////////////////////////////////

#define GeneratedBySisy

#define cpp_Modem

#define SISY_CLASS_NAME Modem

#include "Modem.h"

#include "Controller.h"

#define uartNoTx_

#define uartNoRx_

#define _TheUsic USIC0_CH1

extern  Controller* pGlob_app;

#define app (*pGlob_app)

/////////////////////////////

Modem::Modem()

{

  //  aus Template: PecUart

  // init

  init();

  // config

  #define noBaudrate9600

  #ifndef noBaudrate

    config(9600);

  #endif

}

/////////////////////////////

void Modem::config(uint32_t baudrate, uint8_t dataBits, UartParity parity, UartStopBits stopBits)

{

  //  aus Template: SysUartXmc    GoToSiSy:o:953|zBase:1

  // Disable clock gating to USICn

  #if UC_FAMILY == XMC1

    //SCU_UnlockProtectedBits();  // only for 32 clocks

    SCU_GENERAL->PASSWD = 0x000000C0UL; // disable bit protection

    //SCU_CLK->CGATCLR0 |= SCU_CLK_CGATCLR0_USIC0_Msk;

    SCU_CLOCK_UngateClock( SCU_CLOCK_ID_USIC0 );

    //SCU_LockProtectedBits();

    SCU_GENERAL->PASSWD = 0x000000C3UL; // enable bit protection

  #endif

  // für XMC4

  #if UC_FAMILY == XMC4

    SCU_RESET_ClearResetRequest( SCU_RESET_REQUEST_SOURCE_USIC0 ); 

  #endif

  /* Enable the module kernel clock and the module functionality  */

  _TheUsic->KSCFG |= USIC_CH_KSCFG_MODEN_Msk | USIC_CH_KSCFG_BPMODEN_Msk;

  ////// Baudrate //////

  uint32_t pdiv1 = 1023;    // PDIV = Divider Mode: Divider Factor to Generate, max 10 bit

  uint32_t dctq1 = 16;    // DCTQ = Denominator for Time Quanta Counter, max 5 bit

  uint32_t pctq1 = 1;      // PCTQ = Pre-Divider for Time Quanta Counter, max 2 bit

  if(baudrate>100000)

    dctq1 = 4;

  uint32_t br1=0;

  while(pdiv1>2 && br1<baudrate)

  {

    pdiv1--;

    br1 = SystemCoreClock / (pdiv1*dctq1*pctq1);

  }

  uint32_t fdrStep;  // FDR.STEP = Fractional Divider Register - Step Value, max 10 bit

  fdrStep = 1024*baudrate/br1;

  /* FDR.DM = 02b (Fractional divider mode) */

  uint32_t dm = 0x02;    // Fractional divider mode selected

  if( br1==baudrate )

  {

    dm = 0x01;      // Normal divider mode selected.

    fdrStep = 0x3FF;

  }

  WR_REG(_TheUsic->FDR, USIC_CH_FDR_DM_Msk, USIC_CH_FDR_DM_Pos, dm);

  WR_REG(_TheUsic->FDR, USIC_CH_FDR_STEP_Msk, USIC_CH_FDR_STEP_Pos, fdrStep);

  /* Configure baud rate generator */

  /* BAUDRATE = fCTQIN/(BRG.PCTQ x BRG.DCTQ) */

  /* CLKSEL = 0 (fPIN = fFD), CTQSEL = 00b (fCTQIN = fPDIV), PPPEN = 0 (fPPP=fPIN) */

  uint32_t brg = 0;

  brg |= (pdiv1-1)<<USIC_CH_BRG_PDIV_Pos;

  brg |= (dctq1-1)<<USIC_CH_BRG_DCTQ_Pos;

  brg |= (pctq1-1)<<USIC_CH_BRG_PCTQ_Pos;

  WR_REG(_TheUsic->BRG

    ,USIC_CH_BRG_PCTQ_Msk | USIC_CH_BRG_DCTQ_Msk | USIC_CH_BRG_PDIV_Msk | USIC_CH_BRG_CLKSEL_Msk | USIC_CH_BRG_PPPEN_Msk | USIC_CH_BRG_CTQSEL_Msk

    ,0

    ,brg

    );

  /* Configuration of USIC Shift Control */

    /* SCTR.FLE = 8 (Frame Length) */

    /* SCTR.WLE = 8 (Word Length) */

    /* SCTR.TRM = 1 (Transmission Mode) */

    /* SCTR.PDL = 1 (This bit defines the output level at the shift data output signal when no data is available for transmission) */

  _TheUsic->SCTR &= ~(USIC_CH_SCTR_TRM_Msk | USIC_CH_SCTR_PDL_Msk);

  _TheUsic->SCTR |= (0x01UL << USIC_CH_SCTR_PDL_Pos) | (0x01UL << USIC_CH_SCTR_TRM_Pos);

  // Databits

  WR_REG( _TheUsic->SCTR, USIC_CH_SCTR_FLE_Msk, USIC_CH_SCTR_FLE_Pos, (dataBits-1) );

  WR_REG( _TheUsic->SCTR, USIC_CH_SCTR_WLE_Msk, USIC_CH_SCTR_WLE_Pos, (dataBits-1) );

  /* Configuration of USIC Transmit Control/Status Register */

  /* TBUF.TDEN = 1 (TBUF Data Enable: A transmission of the data word in TBUF can be started if TDV = 1 */

  /* TBUF.TDSSM = 1 (Data Single Shot Mode: allow word-by-word data transmission which avoid sending the same data several times*/

  _TheUsic->TCSR &= ~(USIC_CH_TCSR_TDEN_Msk);

  _TheUsic->TCSR |= USIC_CH_TCSR_TDSSM_Msk | (0x01UL << USIC_CH_TCSR_TDEN_Pos);

  /* Configuration of Protocol Control Register */

    /* PCR.SMD = 1 (Sample Mode based on majority) */

    /* PCR.STPB = 0 (1x Stop bit) */

    /* PCR.SP = <dctq (Sample Point) */

    /* PCR.PL = 0 (Pulse Length is equal to the bit length) */

  _TheUsic->PCR &= ~(USIC_CH_PCR_ASCMode_SP_Msk | USIC_CH_PCR_ASCMode_PL_Msk);

  _TheUsic->PCR |= USIC_CH_PCR_ASCMode_SMD_Msk | ((dctq1/2) << USIC_CH_PCR_ASCMode_SP_Pos);

  // StopBits

  WR_REG(_TheUsic->PCR, USIC_CH_PCR_ASCMode_STPB_Msk, USIC_CH_PCR_ASCMode_STPB_Pos, stopBits);

  /* ----- Configure Transmit Buffer ----- */

  /* Standard transmit buffer event is enabled */

  /* Define start entry of Transmit Data FIFO buffer DPTR = 0*/

  _TheUsic->TBCTR &= ~(USIC_CH_TBCTR_SIZE_Msk | USIC_CH_TBCTR_DPTR_Msk);

  /* Set Transmit Data Buffer to 64 */

  _TheUsic->TBCTR |= 0x06UL << USIC_CH_TBCTR_SIZE_Pos;

  /* Configure Receive Buffer */

  /* Standard receive buffer event is enabled */

  /* Define start entry of Receive Data FIFO buffer DPTR = 0*/

  _TheUsic->RBCTR &= ~(USIC_CH_RBCTR_SIZE_Msk | USIC_CH_RBCTR_DPTR_Msk);

  /* Set Receive Data Buffer to 64 */

  _TheUsic->RBCTR |= 0x06UL << USIC_CH_RBCTR_SIZE_Pos;

  /* ----- Initialize UART_RX (DX0) -----*/

  /* Pin as input */

  {

    SysGpio gpio;

    gpio.init(PORT0, BIT6);

    gpio.setMode(PCx_Input);

  }

  /* Select Pin as input for USIC */

  WR_REG( _TheUsic->DX0CR, USIC_CH_DX0CR_DSEL_Msk, USIC_CH_DX0CR_DSEL_Pos, UsicSelDXnC);

  /* ----- Initialize UART_TX (DOUT) -----*/

  /* Pin as output controlled by ALT7 = U0C1.DOUT0 */

  {

    SysGpio gpio;

    gpio.init(PORT0, BIT7);

    gpio.setMode(PCx_AF7);

  }

  /* Configuration of Channel Control Register */

  /* CCR.PM = 00 ( Disable parity generation) */

  /* CCR.MODE = 2 (ASC mode enabled. Note: 0 (USIC channel is disabled)) */

  // Parity

  WR_REG( _TheUsic->CCR, USIC_CH_CCR_PM_Msk, USIC_CH_CCR_PM_Pos, parity );

  // Uart-Mode

  WR_REG( _TheUsic->CCR, USIC_CH_CCR_MODE_Msk, USIC_CH_CCR_MODE_Pos, 0x02UL );

  // GoToSiSy:d:2477|o:2488|zbase:132

}