SAM4S4C PWM Frequenz

[Fabian K. (farbenjan)]

Hallo,
ich bin langsam am verzweifeln. Ich habe einen SAM4S4C und bekomme als 
max. PWM Frequenz immer nur CPU Takt/100. Im Datenblatt steht aber dass 
die PWM mit dem CPU Takt läuft. Hat jemand von euch Erfahrung mit dem 
Prozessor? Der PMC ist richtig konfiguriert und die im Datenblatt 
angeben Testmethode mit dem auslesen des MAINFRDY Werts ergibt auch 
120Mhz.

gruß Fabian

[Jim M. (turboj)]

Zeig doch mal den Code als Anhang. Meine Glaskugel ist in Reparatur.

[Fabian K. (farbenjan)]

Hier das sollte alles sein was damit in Verbindung steht. Danke

Main.c mit einer PWM
_______________________________________________________________________________________________

  #include "asf.h"
  #include "conf_board.h"
  #include "conf_clock.h"


  #define PWM_DRIVE_FREQUENCY        400000
  #define PWM_DRIVE_PERIOD_VALUE      100
  #define PWM_DRIVE_DUTY_VALUE      50
  #define PWM_DRIVE_CHANNEL        PWM_CHANNEL_0
  #define PWM_CLK_SRC          PWM_CMR_CPRE_MCK  
  pwm_channel_t pwm_drive;


  int main (void)
  {
    board_init();
    sysclk_init();
    pmc_enable_periph_clk(ID_PIOC);
    pmc_enable_periph_clk(ID_PWM);
    pio_set_output(PIOC,PIO_PC11, LOW, DISABLE, ENABLE);
    
    
    pio_set_peripheral(PIOA,PIO_PERIPH_A,PIO_PA0);    
    pwm_channel_disable(PWM, PWM_DRIVE_CHANNEL);
    
    pwm_clock_t clock_setting = {                    
      .ul_clka = PWM_DRIVE_FREQUENCY * PWM_DRIVE_PERIOD_VALUE,
      .ul_clkb = 0,
      .ul_mck =  sysclk_get_cpu_hz()
    };
    pwm_init(PWM, &clock_setting);
    
    pwm_drive.alignment = PWM_ALIGN_LEFT;
    pwm_drive.polarity = PWM_LOW;
    pwm_drive.ul_prescaler = PWM_CLK_SRC; 
    pwm_drive.ul_period = PWM_DRIVE_PERIOD_VALUE;
    pwm_drive.ul_duty = PWM_DRIVE_DUTY_VALUE;
    pwm_drive.channel = PWM_DRIVE_CHANNEL;
    pwm_channel_init(PWM, &pwm_drive);
    pwm_channel_enable(PWM, PWM_DRIVE_CHANNEL);
    
    while (1) {
    }
    
    
  }

  
Der clock_conf Header
_______________________________________________________________________________________________

#ifndef CONF_CLOCK_H_INCLUDED
#define CONF_CLOCK_H_INCLUDED

// ===== System Clock (MCK) Source Options
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_SLCK_RC
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_SLCK_XTAL
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_SLCK_BYPASS
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_4M_RC
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_8M_RC
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_12M_RC
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_XTAL
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_BYPASS
#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_PLLACK
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_PLLBCK

// ===== System Clock (MCK) Prescaler Options   (Fmck = Fsys / (SYSCLK_PRES))
#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_1
//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_2
//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_4
//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_8
//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_16
//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_32
//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_64
//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_3

// ===== PLL0 (A) Options   (Fpll = (Fclk * PLL_mul) / PLL_div)
// Use mul and div effective values here.
#define CONFIG_PLL0_SOURCE          PLL_SRC_MAINCK_XTAL
#define CONFIG_PLL0_MUL             6
#define CONFIG_PLL0_DIV             1
#endif /* CONF_CLOCK_H_INCLUDED */


Und der Clock Treiber
_______________________________________________________________________________________________

#include <sysclk.h>

/// @cond 0
/**INDENT-OFF**/
#ifdef __cplusplus
extern "C" {
#endif
/**INDENT-ON**/
/// @endcond

/**
 * \weakgroup sysclk_group
 * @{
 */

#if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
/**
 * \brief boolean signalling that the sysclk_init is done.
 */
uint32_t sysclk_initialized = 0;
#endif

/**
 * \brief Set system clock prescaler configuration
 *
 * This function will change the system clock prescaler configuration to
 * match the parameters.
 *
 * \note The parameters to this function are device-specific.
 *
 * \param cpu_shift The CPU clock will be divided by \f$2^{mck\_pres}\f$
 */
void sysclk_set_prescalers(uint32_t ul_pres)
{
  pmc_mck_set_prescaler(ul_pres);
  SystemCoreClockUpdate();
}

/**
 * \brief Change the source of the main system clock.
 *
 * \param src The new system clock source. Must be one of the constants
 * from the <em>System Clock Sources</em> section.
 */
void sysclk_set_source(uint32_t ul_src)
{
  switch (ul_src) {
  case SYSCLK_SRC_SLCK_RC:
  case SYSCLK_SRC_SLCK_XTAL:
  case SYSCLK_SRC_SLCK_BYPASS:
    pmc_mck_set_source(PMC_MCKR_CSS_SLOW_CLK);
    break;

  case SYSCLK_SRC_MAINCK_4M_RC:
  case SYSCLK_SRC_MAINCK_8M_RC:
  case SYSCLK_SRC_MAINCK_12M_RC:
  case SYSCLK_SRC_MAINCK_XTAL:
  case SYSCLK_SRC_MAINCK_BYPASS:
    pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK);
    break;

  case SYSCLK_SRC_PLLACK:
    pmc_mck_set_source(PMC_MCKR_CSS_PLLA_CLK);
    break;

  case SYSCLK_SRC_PLLBCK:
    pmc_mck_set_source(PMC_MCKR_CSS_PLLB_CLK);
    break;
  }

  SystemCoreClockUpdate();
}

#if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__)
/**
 * \brief Enable USB clock.
 *
 * \note The SAM3S UDP hardware interprets div as div+1. For readability the hardware div+1
 * is hidden in this implementation. Use div as div effective value.
 *
 * \param pll_id Source of the USB clock.
 * \param div Actual clock divisor. Must be superior to 0.
 */
void sysclk_enable_usb(void)
{
  Assert(CONFIG_USBCLK_DIV > 0);

#ifdef CONFIG_PLL0_SOURCE
  if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL0) {
    struct pll_config pllcfg;

    pll_enable_source(CONFIG_PLL0_SOURCE);
    pll_config_defaults(&pllcfg, 0);
    pll_enable(&pllcfg, 0);
    pll_wait_for_lock(0);
    pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1);
    pmc_enable_udpck();
    return;
  }
#endif

#ifdef CONFIG_PLL1_SOURCE
  if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL1) {
    struct pll_config pllcfg;

    pll_enable_source(CONFIG_PLL1_SOURCE);
    pll_config_defaults(&pllcfg, 1);
    pll_enable(&pllcfg, 1);
    pll_wait_for_lock(1);
    pmc_switch_udpck_to_pllbck(CONFIG_USBCLK_DIV - 1);
    pmc_enable_udpck();
    return;
  }
#endif
}

/**
 * \brief Disable the USB clock.
 *
 * \note This implementation does not switch off the PLL, it just turns off the USB clock.
 */
void sysclk_disable_usb(void)
{
  pmc_disable_udpck();
}
#endif // CONFIG_USBCLK_SOURCE

void sysclk_init(void)
{
  /* Set a flash wait state depending on the new cpu frequency */
  system_init_flash(sysclk_get_cpu_hz());

  /* Config system clock setting */
  if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) {
    osc_enable(OSC_SLCK_32K_RC);
    osc_wait_ready(OSC_SLCK_32K_RC);
    pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
  }

  else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) {
    osc_enable(OSC_SLCK_32K_XTAL);
    osc_wait_ready(OSC_SLCK_32K_XTAL);
    pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
  }

  else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) {
    osc_enable(OSC_SLCK_32K_BYPASS);
    osc_wait_ready(OSC_SLCK_32K_BYPASS);
    pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
  }

  else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) {
    /* Already running from SYSCLK_SRC_MAINCK_4M_RC */
  }

  else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) {
    osc_enable(OSC_MAINCK_8M_RC);
    osc_wait_ready(OSC_MAINCK_8M_RC);
    pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
  }

  else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) {
    osc_enable(OSC_MAINCK_12M_RC);
    osc_wait_ready(OSC_MAINCK_12M_RC);
    pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
  }

  else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) {
    osc_enable(OSC_MAINCK_XTAL);
    osc_wait_ready(OSC_MAINCK_XTAL);
    pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
  }

  else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) {
    osc_enable(OSC_MAINCK_BYPASS);
    osc_wait_ready(OSC_MAINCK_BYPASS);
    pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
  }

#ifdef CONFIG_PLL0_SOURCE
  else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) {
    struct pll_config pllcfg;

    pll_enable_source(CONFIG_PLL0_SOURCE);
    pll_config_defaults(&pllcfg, 0);
    pll_enable(&pllcfg, 0);
    pll_wait_for_lock(0);
    pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES);
  }
#endif

#ifdef CONFIG_PLL1_SOURCE
  else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLBCK) {
    struct pll_config pllcfg;

    pll_enable_source(CONFIG_PLL1_SOURCE);
    pll_config_defaults(&pllcfg, 1);
    pll_enable(&pllcfg, 1);
    pll_wait_for_lock(1);
    pmc_switch_mck_to_pllbck(CONFIG_SYSCLK_PRES);
  }
#endif

  /* Update the SystemFrequency variable */
  SystemCoreClockUpdate();

#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
  /* Signal that the internal frequencies are setup */
  sysclk_initialized = 1;
#endif
}

//! @}

/// @cond 0
/**INDENT-OFF**/
#ifdef __cplusplus
}
#endif
/**INDENT-ON**/
/// @endcond