1 | Main.c mit einer PWM
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2 | _______________________________________________________________________________________________
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3 |
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4 | #include "asf.h"
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5 | #include "conf_board.h"
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6 | #include "conf_clock.h"
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7 |
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8 |
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9 | #define PWM_DRIVE_FREQUENCY 400000
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10 | #define PWM_DRIVE_PERIOD_VALUE 100
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11 | #define PWM_DRIVE_DUTY_VALUE 50
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12 | #define PWM_DRIVE_CHANNEL PWM_CHANNEL_0
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13 | #define PWM_CLK_SRC PWM_CMR_CPRE_MCK
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14 | pwm_channel_t pwm_drive;
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15 |
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16 |
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17 | int main (void)
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18 | {
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19 | board_init();
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20 | sysclk_init();
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21 | pmc_enable_periph_clk(ID_PIOC);
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22 | pmc_enable_periph_clk(ID_PWM);
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23 | pio_set_output(PIOC,PIO_PC11, LOW, DISABLE, ENABLE);
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24 |
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25 |
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26 | pio_set_peripheral(PIOA,PIO_PERIPH_A,PIO_PA0);
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27 | pwm_channel_disable(PWM, PWM_DRIVE_CHANNEL);
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28 |
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29 | pwm_clock_t clock_setting = {
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30 | .ul_clka = PWM_DRIVE_FREQUENCY * PWM_DRIVE_PERIOD_VALUE,
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31 | .ul_clkb = 0,
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32 | .ul_mck = sysclk_get_cpu_hz()
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33 | };
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34 | pwm_init(PWM, &clock_setting);
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35 |
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36 | pwm_drive.alignment = PWM_ALIGN_LEFT;
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37 | pwm_drive.polarity = PWM_LOW;
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38 | pwm_drive.ul_prescaler = PWM_CLK_SRC;
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39 | pwm_drive.ul_period = PWM_DRIVE_PERIOD_VALUE;
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40 | pwm_drive.ul_duty = PWM_DRIVE_DUTY_VALUE;
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41 | pwm_drive.channel = PWM_DRIVE_CHANNEL;
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42 | pwm_channel_init(PWM, &pwm_drive);
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43 | pwm_channel_enable(PWM, PWM_DRIVE_CHANNEL);
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44 |
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45 | while (1) {
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46 | }
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47 |
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48 |
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49 | }
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50 |
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51 |
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52 | Der clock_conf Header
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53 | _______________________________________________________________________________________________
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54 |
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55 | #ifndef CONF_CLOCK_H_INCLUDED
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56 | #define CONF_CLOCK_H_INCLUDED
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57 |
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58 | // ===== System Clock (MCK) Source Options
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59 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC
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60 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL
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61 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS
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62 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC
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63 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC
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64 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC
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65 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL
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66 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS
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67 | #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
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68 | //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLBCK
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69 |
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70 | // ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES))
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71 | #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
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72 | //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2
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73 | //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4
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74 | //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8
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75 | //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16
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76 | //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32
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77 | //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64
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78 | //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3
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79 |
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80 | // ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div)
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81 | // Use mul and div effective values here.
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82 | #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL
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83 | #define CONFIG_PLL0_MUL 6
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84 | #define CONFIG_PLL0_DIV 1
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85 | #endif /* CONF_CLOCK_H_INCLUDED */
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86 |
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87 |
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88 | Und der Clock Treiber
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89 | _______________________________________________________________________________________________
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90 |
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91 | #include <sysclk.h>
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92 |
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93 | /// @cond 0
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94 | /**INDENT-OFF**/
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95 | #ifdef __cplusplus
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96 | extern "C" {
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97 | #endif
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98 | /**INDENT-ON**/
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99 | /// @endcond
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100 |
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101 | /**
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102 | * \weakgroup sysclk_group
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103 | * @{
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104 | */
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105 |
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106 | #if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
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107 | /**
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108 | * \brief boolean signalling that the sysclk_init is done.
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109 | */
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110 | uint32_t sysclk_initialized = 0;
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111 | #endif
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112 |
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113 | /**
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114 | * \brief Set system clock prescaler configuration
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115 | *
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116 | * This function will change the system clock prescaler configuration to
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117 | * match the parameters.
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118 | *
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119 | * \note The parameters to this function are device-specific.
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120 | *
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121 | * \param cpu_shift The CPU clock will be divided by \f$2^{mck\_pres}\f$
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122 | */
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123 | void sysclk_set_prescalers(uint32_t ul_pres)
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124 | {
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125 | pmc_mck_set_prescaler(ul_pres);
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126 | SystemCoreClockUpdate();
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127 | }
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128 |
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129 | /**
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130 | * \brief Change the source of the main system clock.
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131 | *
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132 | * \param src The new system clock source. Must be one of the constants
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133 | * from the <em>System Clock Sources</em> section.
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134 | */
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135 | void sysclk_set_source(uint32_t ul_src)
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136 | {
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137 | switch (ul_src) {
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138 | case SYSCLK_SRC_SLCK_RC:
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139 | case SYSCLK_SRC_SLCK_XTAL:
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140 | case SYSCLK_SRC_SLCK_BYPASS:
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141 | pmc_mck_set_source(PMC_MCKR_CSS_SLOW_CLK);
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142 | break;
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143 |
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144 | case SYSCLK_SRC_MAINCK_4M_RC:
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145 | case SYSCLK_SRC_MAINCK_8M_RC:
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146 | case SYSCLK_SRC_MAINCK_12M_RC:
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147 | case SYSCLK_SRC_MAINCK_XTAL:
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148 | case SYSCLK_SRC_MAINCK_BYPASS:
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149 | pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK);
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150 | break;
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151 |
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152 | case SYSCLK_SRC_PLLACK:
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153 | pmc_mck_set_source(PMC_MCKR_CSS_PLLA_CLK);
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154 | break;
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155 |
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156 | case SYSCLK_SRC_PLLBCK:
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157 | pmc_mck_set_source(PMC_MCKR_CSS_PLLB_CLK);
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158 | break;
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159 | }
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160 |
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161 | SystemCoreClockUpdate();
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162 | }
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163 |
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164 | #if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__)
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165 | /**
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166 | * \brief Enable USB clock.
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167 | *
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168 | * \note The SAM3S UDP hardware interprets div as div+1. For readability the hardware div+1
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169 | * is hidden in this implementation. Use div as div effective value.
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170 | *
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171 | * \param pll_id Source of the USB clock.
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172 | * \param div Actual clock divisor. Must be superior to 0.
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173 | */
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174 | void sysclk_enable_usb(void)
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175 | {
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176 | Assert(CONFIG_USBCLK_DIV > 0);
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177 |
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178 | #ifdef CONFIG_PLL0_SOURCE
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179 | if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL0) {
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180 | struct pll_config pllcfg;
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181 |
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182 | pll_enable_source(CONFIG_PLL0_SOURCE);
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183 | pll_config_defaults(&pllcfg, 0);
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184 | pll_enable(&pllcfg, 0);
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185 | pll_wait_for_lock(0);
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186 | pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1);
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187 | pmc_enable_udpck();
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188 | return;
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189 | }
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190 | #endif
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191 |
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192 | #ifdef CONFIG_PLL1_SOURCE
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193 | if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL1) {
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194 | struct pll_config pllcfg;
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195 |
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196 | pll_enable_source(CONFIG_PLL1_SOURCE);
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197 | pll_config_defaults(&pllcfg, 1);
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198 | pll_enable(&pllcfg, 1);
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199 | pll_wait_for_lock(1);
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200 | pmc_switch_udpck_to_pllbck(CONFIG_USBCLK_DIV - 1);
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201 | pmc_enable_udpck();
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202 | return;
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203 | }
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204 | #endif
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205 | }
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206 |
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207 | /**
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208 | * \brief Disable the USB clock.
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209 | *
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210 | * \note This implementation does not switch off the PLL, it just turns off the USB clock.
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211 | */
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212 | void sysclk_disable_usb(void)
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213 | {
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214 | pmc_disable_udpck();
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215 | }
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216 | #endif // CONFIG_USBCLK_SOURCE
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217 |
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218 | void sysclk_init(void)
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219 | {
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220 | /* Set a flash wait state depending on the new cpu frequency */
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221 | system_init_flash(sysclk_get_cpu_hz());
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222 |
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223 | /* Config system clock setting */
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224 | if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) {
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225 | osc_enable(OSC_SLCK_32K_RC);
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226 | osc_wait_ready(OSC_SLCK_32K_RC);
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227 | pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
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228 | }
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229 |
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230 | else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) {
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231 | osc_enable(OSC_SLCK_32K_XTAL);
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232 | osc_wait_ready(OSC_SLCK_32K_XTAL);
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233 | pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
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234 | }
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235 |
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236 | else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) {
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237 | osc_enable(OSC_SLCK_32K_BYPASS);
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238 | osc_wait_ready(OSC_SLCK_32K_BYPASS);
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239 | pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
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240 | }
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241 |
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242 | else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) {
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243 | /* Already running from SYSCLK_SRC_MAINCK_4M_RC */
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244 | }
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245 |
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246 | else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) {
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247 | osc_enable(OSC_MAINCK_8M_RC);
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248 | osc_wait_ready(OSC_MAINCK_8M_RC);
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249 | pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
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250 | }
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251 |
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252 | else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) {
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253 | osc_enable(OSC_MAINCK_12M_RC);
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254 | osc_wait_ready(OSC_MAINCK_12M_RC);
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255 | pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
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256 | }
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257 |
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258 | else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) {
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259 | osc_enable(OSC_MAINCK_XTAL);
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260 | osc_wait_ready(OSC_MAINCK_XTAL);
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261 | pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
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262 | }
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263 |
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264 | else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) {
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265 | osc_enable(OSC_MAINCK_BYPASS);
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266 | osc_wait_ready(OSC_MAINCK_BYPASS);
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267 | pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
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268 | }
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269 |
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270 | #ifdef CONFIG_PLL0_SOURCE
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271 | else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) {
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272 | struct pll_config pllcfg;
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273 |
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274 | pll_enable_source(CONFIG_PLL0_SOURCE);
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275 | pll_config_defaults(&pllcfg, 0);
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276 | pll_enable(&pllcfg, 0);
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277 | pll_wait_for_lock(0);
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278 | pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES);
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279 | }
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280 | #endif
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281 |
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282 | #ifdef CONFIG_PLL1_SOURCE
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283 | else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLBCK) {
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284 | struct pll_config pllcfg;
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285 |
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286 | pll_enable_source(CONFIG_PLL1_SOURCE);
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287 | pll_config_defaults(&pllcfg, 1);
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288 | pll_enable(&pllcfg, 1);
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289 | pll_wait_for_lock(1);
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290 | pmc_switch_mck_to_pllbck(CONFIG_SYSCLK_PRES);
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291 | }
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292 | #endif
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293 |
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294 | /* Update the SystemFrequency variable */
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295 | SystemCoreClockUpdate();
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296 |
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297 | #if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
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298 | /* Signal that the internal frequencies are setup */
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299 | sysclk_initialized = 1;
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300 | #endif
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301 | }
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302 |
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303 | //! @}
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304 |
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305 | /// @cond 0
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306 | /**INDENT-OFF**/
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307 | #ifdef __cplusplus
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308 | }
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309 | #endif
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310 | /**INDENT-ON**/
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311 | /// @endcond
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