Blockram Template

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;

use UNISIM.VComponents.all;

entity x_blockram is

      Port( DOA     : out std_logic_vector(1 to 32);        -- Port A

32-bit Data Output

          DOB     : out std_logic_vector(1 to 32);        -- Port B 32-bit

Data Output

          DOPA     : out std_logic_vector(1 to 4);        -- Port A 4-bit

Parity Output

           DOPB     : out std_logic_vector(1 to 4);        -- Port B 4-bit

Parity Output

          ADDRA   : in std_logic_vector(8 downto 0);      -- Port A 9-bit

Address Input

          ADDRB   : in std_logic_vector(8 downto 0);     -- Port B 9-bit

Address Input

            CLKA     : in std_logic;                

          CLKB     : in std_logic;                -- Port B Clock

            DIA     : in std_logic_vector(1 to 32);        -- Port A 32-bit

Data Input

          DIB     : in std_logic_vector(1 to 32);        -- Port B 32-bit

Data Input

          DIPA     : in std_logic_vector(1 to 4);        -- Port A 4-bit

parity Input

          DIPB     : out std_logic_vector(1 to 4);        -- Port-B 4-bit

parity Input

          ENA     : in std_logic;                  -- Port A RAM Enable Input

          ENB     : in std_logic;                -- PortB RAM Enable Input

          SSRA     : in std_logic;                  -- Port A Synchronous

Set/Reset Input

          SSRB     : in std_logic;                  -- Port B Synchronous

Set/Reset Input

          WEA     : in std_logic;                    -- Port A Write Enable Input

          WEB     : in std_logic); 

end x_blockram;

architecture Behavioral of x_blockram is

   -- RAMB16_S36_S36: Virtex-II/II-Pro, Spartan-3/3E 512 x 32 + 4

Parity bits Dual-Port RAM

   -- Xilinx  HDL Language Template version 7.1i

RAMB16_S36_S36_inst : RAMB16_S36_S36

   generic map (

      INIT_A => X"000000000",  --  Value of output RAM registers on

Port A at startup

      INIT_B => X"000000000",  --  Value of output RAM registers on

Port B at startup

      SRVAL_A => X"000000000", --  Port A ouput value upon SSR

assertion

      SRVAL_B => X"000000000", --  Port B ouput value upon SSR

assertion

      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or

NO_CHANGE

      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or

NO_CHANGE

      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING",

"GENERATE_X_ONLY", "ALL" 

      INIT_00 =>

X"0000000000000000000000000000000000000000000000000000000000000000",