Gast
#252804
Guten Morgen, habe ein Problem mit einem kleinen Testprogram. Bitte nicht lachen, fange gerade an. Der Compiler meckert die Zeile "if CLOCK='1' and CLOCK'event then" mit dem Fheler HDLParser808 an. Kann mir bitte jmd. sagen wo das Problem liegt? (Xilinx ISE, VHDL-Top-Level_Module) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.std_logic_unsigned.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity Counter is Port ( CLOCK : in std_logic_vector(0 downto 0); DIRECTION : in std_logic_vector(0 downto 0); COUNT_OUT : out std_logic_vector(3 downto 0)); end Counter; architecture Behavioral of counter is signal count_int : std_logic_vector(0 to 3) := "0000"; begin process (CLOCK) begin if CLOCK='1' and CLOCK'event then if DIRECTION='1' then count_int <= count_int + 1; else count_int <= count_int - 1; end if; end if; end process; COUNT_OUT <= count_int; end Behavioral;