typconveting std_logic_vektor => int

ich muss eine typumwandlung mache leider bin ich anfänger und verzweifle
daran. das macht probleme:conv_unsigned(colume,8)
ich will eine std_logic_vektor in ein int umwandeln, ws mach ich
falsch?



ENTITY del_old_pixel IS
   PORT(
      avarage      : IN     std_logic_vector (8 DOWNTO 0);
      colume       : IN     std_logic_vector (8 DOWNTO 0);
      line_start   : IN     std_logic_vector ( 8 DOWNTO 0 );
      new_data_clk : IN     std_logic;
      reset        : IN     std_logic;
      sys_clk      : IN     std_logic;
      column_del   : OUT    std_logic_vector ( 9 DOWNTO 0 );
      line_del     : OUT    std_logic_vector ( 9 DOWNTO 0 )
   );

-- Declarations

END del_old_pixel ;




ARCHITECTURE behav OF del_old_pixel IS

  type  MEMORY is array (0 to 489) of std_logic_vector (8 DOWNTO 0);
  Signal colum_ram: MEMORY;
  Signal l_tmp: std_logic_vector (9 DOWNTO 0);


BEGIN
  process(sys_clk,reset)
    variable old : std_logic;
     begin
      if(reset='0') then
         old := '0';


      elsif (sys_clk = '1'and sys_clk'event)then
        if(old='0' and new_data_clk ='1')then
           l_tmp <= ('0'&line_start)
+('0'&colum_ram(conv_integer(colume,8)));
           colum_ram(conv_unsigned(colume,8))<= avarage;


        end if;
          old :=new_data_clk;
      else
        old :=new_data_clk;
      end if;

  end process;
  line_del <=l_tmp;



END ARCHITECTURE behav;