STM32f2 ADC + DMA

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void init_a2d_1(void) {

  int i = 0;

  /*****  Clock_init  *****/

  rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); /**< Enable internal clock APB2 (60MHZ) for ADC1 */

  rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC2EN); /**< Enable internal clock APB2 (60MHZ) for ADC2 */

  //rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPAEN); /**< Enable internal clock AHB1 (120MHZ) for analog-input Port A */

  //rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPCEN); /**< Enable internal clock AHB1 (120MHZ) for analog-input Port C */

  rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_DMA2EN); /**< Enable internal clock AHB1 (120MHZ) for DMA2 */

  /*++++++++++++++++++++ gpio_a ++++++++++++++++++++*/

  /*****  Analog, no push/pull to HI or LOW  *****/

  gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO5 | GPIO6 | GPIO7);  //optPower, temp1+2

  gpio_mode_setup(GPIOC, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO0 | GPIO4);      //stackVoltage, hum

  /***** enable DMA and config *****/

#ifdef DMA_ON

  /**

   * Reference manual 10.9

   *    DMA mode 2: on the first request ADC2 and ADC1 are transfered

   *    (ADC2 data take the upper half-word and ADC1 data take the lower half-word)

   */

  dma_setup();

  nvic_enable_irq(NVIC_DMA2_STREAM0_IRQ);

  nvic_set_priority(NVIC_DMA2_STREAM0_IRQ, configMAX_SYSCALL_INTERRUPT_PRIORITY);

  nvic_enable_irq(NVIC_DMA2_STREAM2_IRQ);

  nvic_set_priority(NVIC_DMA2_STREAM2_IRQ, configMAX_SYSCALL_INTERRUPT_PRIORITY);

#endif  // DMA_ON

  /********** SINGLE MODE -> ADC1 ***********/

  /*****  Make sure the ADC doesn't run during config  *****/

  adc_off(ADC1);

  adc_off(ADC2);

  /*****  12-bit  *****/

  adc_set_resolution(ADC1, ADC_CR1_RES_12BIT);

  adc_set_resolution(ADC2, ADC_CR1_RES_12BIT);

  /*****  Prescaler 60MHZ/By2 = 30MHZ  *****/

  adc_set_clk_prescale(ADC_CCR_ADCPRE_BY2);

#ifdef DMA_ON

  adc_enable_scan_mode(ADC1);

  adc_enable_scan_mode(ADC2);

//  adc_set_single_conversion_mode(ADC1);

//  adc_set_single_conversion_mode(ADC2);

  adc_set_continuous_conversion_mode(ADC1);

  adc_set_continuous_conversion_mode(ADC2);

  /***** Trigger none *****/

  adc_disable_external_trigger_regular(ADC1);

  adc_disable_external_trigger_regular(ADC2);

#else

  adc_set_single_conversion_mode(ADC1);

  adc_set_single_conversion_mode(ADC2);

#endif  // DMA_ON

  /***** result is stored right-aligned *****/

  adc_set_right_aligned(ADC1); //The result is right_aligned in a 32bit result-register

  adc_set_right_aligned(ADC2); //The result is right_aligned in a 32bit result-register

  /***** sampling_time from ADC *****/

  /* Fast_convertion at 3CYC by reducing the resolution, 28CYC sampletime is much more precise */

  //adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_112CYC);

  //adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_56CYC);

  //adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_28CYC);

  adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_15CYC);

  adc_set_sample_time_on_all_channels(ADC2, ADC_SMPR_SMP_15CYC);

  //adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_3CYC);

  /***** eoc interrupt *****/

  adc_enable_eoc_interrupt(ADC1);    //Interrupt

  adc_enable_eoc_interrupt(ADC2);

  uint8_t groupOfChannnels1[3];

  groupOfChannnels1[0] = ADC_CHANNEL6;  //ADC1

  groupOfChannnels1[1] = ADC_CHANNEL7;  //ADC1

  groupOfChannnels1[2] = ADC_CHANNEL5;  //ADC1

  /***** regular group (channel selection) *****/

  adc_set_regular_sequence(ADC1, 3, groupOfChannnels1);

  uint8_t groupOfChannnels2[3];

  groupOfChannnels2[0] = ADC_CHANNEL10;  //ADC2

  groupOfChannnels2[1] = ADC_CHANNEL14;  //ADC2

  groupOfChannnels2[2] = ADC_CHANNEL10;  //ADC2

  /***** regular group (channel selection) *****/

  adc_set_regular_sequence(ADC2, 3, groupOfChannnels2);

  /*****  ADC2 for DualMode - activate DualMode just before start ADC1+2 *****/

  /********* DUAL MODE -> ADC1 + ADC2 *********/

  /***** Dual mode: regular simultaneous mode *****/

  adc_set_multi_mode(ADC_CCR_MULTI_DUAL_REGULAR_SIMUL);

  /***** Start ADC *****/

  adc_power_on(ADC1);

  adc_power_on(ADC2);

  /***** Wait for ADC is up *****/

  for (i = 0; i < 800000; i++) /* Wait a bit. */

    __asm__("nop");

  /***** Start conversion (in simultaneous-mode only ADC1 to be triggered) *****/

  adc_start_conversion_regular(ADC1);

  /***** NVIC interrupt ADC *****/

//  nvic_enable_irq(NVIC_ADC_IRQ);

//  nvic_set_priority(NVIC_ADC_IRQ, configMAX_SYSCALL_INTERRUPT_PRIORITY);

}

/**

 *  DMA setup for ADC conversion

 *

 *    DMA2 -  For ADC-converter you must use the DMA2 (Reference Manual 9.3.3)

 *        and make sure, you are using the right streams and channels

 *

 *     ADC1: DMA2, Channel0, Stream0 and Stream4

 *     ADC2: DMA2, Channel1, Stream2 and Stream3

 *     ADC3: DMA2, Channel2, Stream0 and Stream1

 *

 */

void dma_setup() {

  /**

   *  DMA Stream

   *     - Init-procedure is shown in Reference Manual 9.3.17

   *

   *     Check:

   *     - Step 4. Number of data

   */

  /***************************** Stream configuration procedure **********************************/

  extern ringbufferOUTadc2[3];

  extern ringbufferOUTadc1[3];

  extern ringbufferINadc2[3];

  extern ringbufferINadc1[3];

  dma_stream_reset(DMA2, DMA_STREAM0);

  dma_stream_reset(DMA2, DMA_STREAM2);

  /***** first step, disable streams. Last step, enable stream again! *****/

  dma_disable_stream(DMA2, DMA_STREAM0);

  dma_disable_stream(DMA2, DMA_STREAM2);

  // 2. Set the peripheral port register address in the DMA_SxPAR register. The

  // data will be moved from/ to this address to/ from the peripheral port

  // after the peripheral event.

//  dma_set_peripheral_address(DMA2, DMA_STREAM0, (uint32_t) &DMA_SPAR(DMA_STREAM0, 3) );

//  dma_set_peripheral_address(DMA2, DMA_STREAM2, (uint32_t) &DMA_SPAR(DMA_STREAM2, 3) );

  dma_set_peripheral_address(DMA2, DMA_STREAM0, (uint32_t) ringbufferINadc1);

  dma_set_peripheral_address(DMA2, DMA_STREAM2, (uint32_t) ringbufferINadc2);

  // 3. Set the memory address in the DMA_SxMA0R register (and in the DMA_SxMA1R

  // register in the case of a double buffer mode). The data will be written

  // to or read from this memory after the peripheral event.

//  dma_set_memory_address(DMA2, DMA_STREAM0, (uint32_t) &DMA_SM0AR(DMA_STREAM0, 3) );

//  dma_set_memory_address(DMA2, DMA_STREAM2, (uint32_t) &DMA_SM0AR(DMA_STREAM2, 3) );

  dma_set_memory_address(DMA2, DMA_STREAM0, (uint32_t) &ringbufferOUTadc1);

  dma_set_memory_address(DMA2, DMA_STREAM2, (uint32_t) &ringbufferOUTadc2);

  // 4. Configure the total number of data items to be transferred in the

  // DMA_SxNDTR register. After each peripheral event or each beat of the

  // burst, this value is

  // decremented.

  dma_set_number_of_data(DMA2, DMA_STREAM0, 3);

  dma_set_number_of_data(DMA2, DMA_STREAM2, 3);

  // 5. Select the DMA channel (request) using CHSEL[2:0] in the DMA_SxCR

  // register.

  dma_channel_select(DMA2, DMA_STREAM0, DMA_SxCR_CHSEL_0);

  dma_channel_select(DMA2, DMA_STREAM2, DMA_SxCR_CHSEL_1);

  // 6. If the peripheral is intended to be the flow controller and if it

  // supports this feature, set the PFCTRL bit in the DMA_SxCR register.

  // Nope

  // 7. Configure the stream priority using the PL[1:0] bits in the DMA_SxCR

  // register.

  dma_set_priority(DMA2, DMA_STREAM0, DMA_SxCR_PL_MEDIUM);

  dma_set_priority(DMA2, DMA_STREAM2, DMA_SxCR_PL_MEDIUM);

  // 8. Configure the FIFO usage (enable or disable, threshold in transmission

  // and reception) Leave as default (direct mode)

  // 9. Configure the:

  // - data transfer direction,

  dma_set_transfer_mode(DMA2, DMA_STREAM0, DMA_SxCR_DIR_PERIPHERAL_TO_MEM);

  dma_set_transfer_mode(DMA2, DMA_STREAM2, DMA_SxCR_DIR_PERIPHERAL_TO_MEM);

  // - peripheral and memory incremented/fixed mode,

  dma_disable_peripheral_increment_mode(DMA2, DMA_STREAM0);

  dma_disable_peripheral_increment_mode(DMA2, DMA_STREAM2);

  dma_enable_memory_increment_mode(DMA2, DMA_STREAM0);

  dma_enable_memory_increment_mode(DMA2, DMA_STREAM2);

  // - single or burst transactions,

  // Single is default

  // - peripheral and memory data widths,

  dma_set_memory_size(DMA2, DMA_STREAM0, DMA_SxCR_MSIZE_32BIT);

  dma_set_memory_size(DMA2, DMA_STREAM2, DMA_SxCR_MSIZE_32BIT);

  dma_set_peripheral_size(DMA2, DMA_STREAM0, DMA_SxCR_PSIZE_16BIT);

  dma_set_peripheral_size(DMA2, DMA_STREAM2, DMA_SxCR_PSIZE_16BIT);

  // - Circular mode, DMA-controller starts from base-address when internal counter reached 0

  dma_enable_circular_mode(DMA2, DMA_STREAM0);

  dma_enable_circular_mode(DMA2, DMA_STREAM2);

  // - Double buffer mode

  // Not enabled

  // - interrupts after half and/or full transfer,

//  ADC_MultiModeDMARequestAfterLastTransferCmd(ENABLE);

  // Not yet...

  // - and/or errors in the DMA_SxCR register.

  // Not yet...

  /***** Last step: enable streams again. Activate the stream by setting the EN bit in the DMA_SxCR register. *****/

  dma_enable_stream(DMA2, DMA_STREAM0);

  dma_enable_stream(DMA2, DMA_STREAM2);

  /***** Enable DMA for ADC1, ADC2, ADC3 *****/

  adc_enable_dma(ADC1);

  adc_enable_dma(ADC2);

  /***** Set DMA to Continue *****/

//  adc_set_dma_continue(ADC1);

//  adc_set_dma_continue(ADC2);

//    /*****  select channel for ADC1, ADC2, ADC3  *****/

//    dma_channel_select(DMA2, DMA_STREAM0, 0);

//    dma_channel_select(DMA2, DMA_STREAM2, 1);

}

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uint16_t ringbufferOUTadc1[3] = { 0xAAAA, 0xAAAA, 0xAAAA };

uint16_t ringbufferOUTadc2[3] = { 0xBBBB, 0xBBBB, 0xBBBB };

uint16_t ringbufferINadc1[3];

uint16_t ringbufferINadc2[3];

uint32_t raw_value, test;

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/**

 * TSK_ReadSensor

 *

 * Read adc inputs

 *

 * @param pvParameters

 */

void TSK_ReadSensor(void *pvParameters) {

  int idx, k = 0;

  uint16_t valueADC1, valueADC2, valueADC3, valueADC4, valueADC5, valueADC6;

  for (;;) {

//      raw_value = adc_read_regular(ADC1);

//      test = raw_value;

//        while (!(adc_eoc(ADC1)))

//          ;

//      valueADC1 = raw_value;

//      valueADC2 = raw_value >> 16;

        /***** read analog values *****/

        ringbufferOUTadc1[k] = ringbufferINadc1[k];

        ringbufferOUTadc2[k] = ringbufferINadc2[k];

        k++;

  }

}