1 | void
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2 | Uart_Init(void)
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3 | {
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4 | // enable UART and GPIO port A
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5 | SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
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6 | SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
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7 | // init FIFOs
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8 | FifoQueue_Init(&g_sUartRxFifo,UART_RX_FIFO_SIZE);
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9 | FifoQueue_Init(&g_sUartTxFifo,UART_TX_FIFO_SIZE);
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10 | // set GPIO ports
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11 | GPIOPinConfigure(GPIO_PA0_U0RX);
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12 | GPIOPinConfigure(GPIO_PA1_U0TX);
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13 | GPIOPinTypeUART(GPIO_PORTA_BASE,GPIO_PIN_0 | GPIO_PIN_1);
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14 | // disable UART
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15 | // UARTDisable(UART0_BASE);
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16 | // set UART clock
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17 | UARTConfigSetExpClk(UART0_BASE,SysCtlClockGet(),115200,(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
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18 | // disable FIFOs
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19 | UARTFIFODisable(UART0_BASE);
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20 | // enable RX and disable TX interrupt
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21 | IntEnable(INT_UART0);
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22 | UARTIntEnable(UART0_BASE,UART_INT_RX);
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23 | UARTIntDisable(UART0_BASE,UART_INT_TX);
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24 | // enable UART
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25 | // UARTEnable(UART0_BASE);
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26 | }
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27 |
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28 | void
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29 | Uart0_Isr(void)
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30 | {
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31 | uint32_t status;
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32 | // get status
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33 | status = UARTIntStatus(UART0_BASE,true);
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34 | // clear status
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35 | UARTIntClear(UART0_BASE,status);
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36 | // RX interrupt?
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37 | if(status & UART_INT_RX)
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38 | {
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39 | while(UARTCharsAvail(UART0_BASE)) //loop while there are chars
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40 | {
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41 | char chr = UARTCharGetNonBlocking(UART0_BASE);
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42 | // push character into fifo queue
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43 | FifoQueue_Push(&g_sUartRxFifo,chr);
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44 | }
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45 | }
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46 | // TX interrupt?
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47 | if(status & UART_INT_TX)
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48 | {
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49 | while(FifoQueue_ItemAvailable(&g_sUartTxFifo) && UARTSpaceAvail(UART0_BASE))
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50 | {
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51 | char chr;
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52 | // pop character from fifo and put it into the UART fifo
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53 | FifoQueue_Pop(&g_sUartTxFifo,(uint8_t*)&chr);
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54 | UARTCharPutNonBlocking(UART0_BASE,chr);
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55 | }
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56 | // check if we need another interrupt
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57 | if(!FifoQueue_ItemAvailable(&g_sUartTxFifo))
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58 | {
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59 | // disable UART TX interrupt
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60 | UARTIntDisable(UART0_BASE,UART_INT_TX);
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61 | }
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62 |
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63 | g_sUartTxIntOccured = true;
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64 | }
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65 | }
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66 |
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67 | void
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68 | Uart0_SendBuffer(char* buffer,
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69 | uint16_t size)
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70 | {
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71 | uint16_t pos = 0;
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72 | // go through the buffer
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73 | while(pos < size)
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74 | {
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75 | // disable TX interrupt
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76 | UARTIntDisable(UART0_BASE,UART_INT_TX);
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77 | // if the FIFO is full, we need to wait
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78 | if(FifoQueue_IsFull(&g_sUartTxFifo))
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79 | {
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80 | g_sUartTxIntOccured = false;
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81 | // enable interrupts
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82 | UARTIntEnable(UART0_BASE,UART_INT_TX);
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83 | // wait for interrupt
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84 | while(!g_sUartTxIntOccured)
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85 | {
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86 | ;
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87 | }
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88 | // disable interrupts
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89 | UARTIntDisable(UART0_BASE,UART_INT_TX);
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90 | }
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91 | // push characters into the FIFO
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92 | while(pos < size && !FifoQueue_IsFull(&g_sUartTxFifo))
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93 | {
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94 | FifoQueue_Push(&g_sUartTxFifo,buffer[pos++]);
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95 | }
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96 | // enable interrupts
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97 | UARTIntEnable(UART0_BASE,UART_INT_TX);
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98 | }
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99 | }
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100 |
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101 | bool
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102 | Uart0_CharAvailable(void)
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103 | {
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104 | return (g_sUartRxFifo.header.numItems > 0);
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105 | }
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106 |
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107 | char
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108 | Uart0_GetChar(void)
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109 | {
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110 | char chr = 0;
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111 | // disable interrupts
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112 | UARTIntDisable(UART0_BASE,UART_INT_RX);
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113 | // get character
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114 | if(g_sUartRxFifo.header.numItems > 0)
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115 | {
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116 | FifoQueue_Pop(&g_sUartRxFifo,(uint8_t*)&chr);
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117 | }
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118 | // enable interrupts
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119 | UARTIntEnable(UART0_BASE,UART_INT_RX);
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120 |
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121 | return chr;
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122 | }
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