I have a $18
ALTERA-FPGA-Cyclone-II-EP2C5T144-Minimum-System-Development-Board
http://www.ebay.com/itm/201070505640
I can get Quartus t build the DE1 procject with the above FPGA if i
reduce the Ram from 32K to 8K.
1 | Flow Status Successful - Sun Dec 21 21:44:14 2014
|
2 | Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
3 | Revision Name ByteGenerator
|
4 | Top-level Entity Name ByteGenerator
|
5 | Family Cyclone II
|
6 | Device EP2C5T144C8
|
7 | Timing Models Final
|
8 | Total logic elements 1,996 / 4,608 ( 43 % )
|
9 | Total combinational functions 1,925 / 4,608 ( 42 % )
|
10 | Dedicated logic registers 323 / 4,608 ( 7 % )
|
11 | Total registers 323
|
12 | Total pins 50 / 89 ( 56 % )
|
13 | Total virtual pins 0
|
14 | Total memory bits 65,536 / 119,808 ( 55 % )
|
15 | Embedded Multiplier 9-bit elements 0 / 26 ( 0 % )
|
16 | Total PLLs 0 / 2 ( 0 % )
|
In : Microcomputer_Module.vhd
Change the Ram_Array
-- Memory Array Types
---------------------------------------------------------------
type RAM_Array is array (0 to 8191) of std_logic_vector(7 downto 0);
type ROM_Array is array (0 to 359) of std_logic_vector(7 downto 0);
The MCU is apparently based on the T80 (Original file Name: "T80.vhd")
-- This VHDL code describes the core of the DMC8 microprocessor,
-- a modified and reduced version of the original Z80 microprocessor
The first op is to load the stack
START: LD SP,0FFFFh ;stack pointer initialization
And ah there is 32K ROM & 32K RAM in the DCM8 uC , i expect the ram to
start @32K. But i haven't got the VHDL knowledge to verify it.
If the above is correct , this means i should loat the SP with 32K+8K-1
= 09FFFh
Dammm ... Why didn't i bring my cheap fpga board with me :-(
Well hope someone wants to "play along"
/Bingo
