DEEDS logic simulator & VHDL code generator

[Karsten F. (Firma: von Dänemark) (bingo600)]

I'm a VHDL Beginner , and just found DEEDS  (Run's ok in linux wine)

It's a Logic simulator , and VHDL code generator with a littlt MCU built 
in.

http://www.esng.dibe.unige.it/Deeds/

Just tried the one attached (added the missing Assembler code, as its 
for learning)
http://www.esng.dibe.unige.it/Deeds/LearningMaterials/LM/T110/110043_Byte_Generator_On_FPGA/Index.htm


Orig code  :
http://www.esng.dibe.unige.it/Deeds/LearningMaterials/LM/T110/110043.zip

Current projects:
http://www.esng.dibe.unige.it/Deeds/LearningMaterials/IndexByTopic.htm


It's clearly a learning tool , but quite fun to play with.
I haven't tried it on "Silicon" as im in the summerhouse don't have any 
HW with me.


Maybe Lothar (or another "guru" could have a look :-)

The attached code contains the project, assembler and VHDL

mfg
Bingo

[Karsten F. (Firma: von Dänemark) (bingo600)]

Hmmm ...

Additional Info.

The above attached VHDL isn't complete.

I just tried the "Test on FPGA" , and that one generates full quartus 
projects , for either Altera DE1 or DE2 (attached).

I justtried the DE2 , it can be syhthezised w. Quartus.

So i guess it's mostly a Quartus tool (if you're a beginner, like me)

Bingo

[Karsten F. (Firma: von Dänemark) (bingo600)]

I have a $18
ALTERA-FPGA-Cyclone-II-EP2C5T144-Minimum-System-Development-Board
http://www.ebay.com/itm/201070505640

I can get Quartus t build the DE1 procject with the above FPGA if i 
reduce the Ram from 32K to 8K.

Flow Status  Successful - Sun Dec 21 21:44:14 2014
Quartus II 64-Bit Version  13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name  ByteGenerator
Top-level Entity Name  ByteGenerator
Family  Cyclone II
Device  EP2C5T144C8
Timing Models  Final
Total logic elements  1,996 / 4,608 ( 43 % )
Total combinational functions  1,925 / 4,608 ( 42 % )
Dedicated logic registers  323 / 4,608 ( 7 % )
Total registers  323
Total pins  50 / 89 ( 56 % )
Total virtual pins  0
Total memory bits  65,536 / 119,808 ( 55 % )
Embedded Multiplier 9-bit elements  0 / 26 ( 0 % )
Total PLLs  0 / 2 ( 0 % )

In : Microcomputer_Module.vhd

Change the Ram_Array

  -- Memory Array Types 
---------------------------------------------------------------
  type RAM_Array is array (0 to 8191) of std_logic_vector(7 downto 0);
  type ROM_Array is array (0 to 359) of std_logic_vector(7 downto 0);


The MCU is apparently based on the T80 (Original file Name: "T80.vhd")
-- This VHDL code describes the core of the DMC8 microprocessor,
-- a modified and reduced version of the original Z80 microprocessor

The first op is to load the stack
START:  LD  SP,0FFFFh  ;stack pointer initialization

And ah there is 32K ROM & 32K RAM in the DCM8 uC , i expect the ram to 
start @32K. But i haven't got the VHDL knowledge to verify it.

If the above is correct , this means i should loat the SP with 32K+8K-1 
= 09FFFh

Dammm ... Why didn't i bring my cheap fpga board with me :-(

Well hope someone wants to "play along"

/Bingo