TWIM mit AT32UC3C

uint8_t data[1] = { 0 };

twim_write (twim,data,0,chip_addr,0);

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status_code_t twim_write (volatile avr32_twim_t *twim, uint8_t const *buffer,

    uint32_t nbytes, uint32_t saddr, bool tenbit)

{

  // Reset the TWIM module to clear the THR register

  twim->cr = AVR32_TWIM_CR_MEN_MASK;

  twim->cr = AVR32_TWIM_CR_SWRST_MASK;

  twim->cr = AVR32_TWIM_CR_MDIS_MASK;

  // Set pointer to TWIM instance for IT

  twim_inst = twim;

  // Disable the TWIM interrupts

  twim_disable_interrupt (twim_inst);

  // get a pointer to applicative data

  twim_tx_data = buffer;

  // set the number of bytes to transmit

  twim_tx_nb_bytes = nbytes;

  // Set next transfer to false

  twim_next = false;

  // Initialize bus transfer status

  transfer_status = TWI_SUCCESS;

  // set the command to start the transfer

  twim_inst->cmdr = (saddr << AVR32_TWIM_CMDR_SADR_OFFSET)

      | (nbytes << AVR32_TWIM_CMDR_NBYTES_OFFSET)

      | (AVR32_TWIM_CMDR_VALID_MASK)

      | (AVR32_TWIM_CMDR_START_MASK)

      | (AVR32_TWIM_CMDR_STOP_MASK)

      | ((tenbit ? 1 : 0) << AVR32_TWIM_CMDR_TENBIT_OFFSET)

      | (0 << AVR32_TWIM_CMDR_READ_OFFSET);

  // mask NACK and TXRDY interrupts

  twim_it_mask = AVR32_TWIM_IER_NAK_MASK | AVR32_TWIM_IER_TXRDY_MASK;

  // update IMR through IER

  twim_inst->ier = twim_it_mask;

  // Enable master transfer

  twim_inst->cr = AVR32_TWIM_CR_MEN_MASK;

  // Enable all interrupts

  cpu_irq_enable ();

  // send data

  while (!(transfer_status) && !(twim_status ())) {

    cpu_relax();

  }

#if AVR32_TWIM_H_VERSION > 101  // Removed in twim100 module due to IC bug

  // Disable master transfer

  twim->cr = AVR32_TWIM_CR_MDIS_MASK;

#endif

  if (transfer_status == TWI_RECEIVE_NACK

      || transfer_status == TWI_ARBITRATION_LOST) {

    return ERR_IO_ERROR;

  }

  return STATUS_OK;

}