VHDL Timer & PWM

Daniel K. (daniel_k80) OP 24.02.2015 12:27 #4026606

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Hallo zusammen,

ich habe meine Timer + PWM Schaltung fertig gemacht und möchte die im 
nächsten Schritt in einen IP-Core gießen um die dann per AXI in meinem 
Zynq zu verwenden.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- Create Date:         10.02.2015 11:18:22
-- Design Name: 
-- Module Name:         PWM - PWM_Arch
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description:         Simple Timer & PWM Module
-- Dependencies: 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_unsigned.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Timer is
    Generic (   Width : integer := 8 );
    Port (      Clock_In : in STD_LOGIC;
                Prescaler : in STD_LOGIC_VECTOR(2 downto 0);
                Preload : in STD_LOGIC_VECTOR(Width - 1 downto 0);
                Capture : in STD_LOGIC_VECTOR(Width - 1 downto 0);
                Reset : in STD_LOGIC := '1';
                PWM_Enable : in STD_LOGIC := '0';
                PWM_Inv : in STD_LOGIC := '0';
                Compare : out STD_LOGIC := '0';
                Overflow : out STD_LOGIC := '0';
                PWM : out STD_LOGIC := '0';
                Clock_Out : out STD_LOGIC); 
end Timer;
architecture Timer_Arch of Timer is
    signal Clock_Intern : std_logic;
    signal Counter      : std_logic_vector(Width - 1 downto 0) :=  (others => '0');
    signal Counter_Timer: std_logic_vector(Width - 1 downto 0) :=  (others => '0');
    -- Prescaler
    process(Clock_In, Reset, Prescaler)
    begin
        if(Reset = '1') then
            Counter <= (others => '0');
        elsif(rising_edge(Clock_In)) then
            Counter <= Counter + 1;
        end if;
        case Prescaler is
            when "001" => Clock_Intern <= Counter(1);
            when "010" => Clock_Intern <= Counter(2);
            when "011" => Clock_Intern <= Counter(3);
            when "100" => Clock_Intern <= Counter(4);
            when "101" => Clock_Intern <= Counter(5);
            when "110" => Clock_Intern <= Counter(6);
            when "111" => Clock_Intern <= Counter(7);
            when others => Clock_Intern <= Counter(0);
        end case;        
    end process;
    process
    begin    
        wait until(rising_edge(Clock_Intern)); 
            Counter_Timer <= Counter_Timer + 1;
        if(PWM_Enable = '0') then
            -- Compare Interrupt
            if(Counter_Timer(Width - 1 downto 0) > (Preload(Width - 1 downto 0) - 1)) then
                Compare <= '1';
                Counter_Timer <= (others => '0');
            else
                Compare <= '0';
            end if;
            -- Overflow Interrupt
            if(Counter_Timer = ((2**Width) - 1)) then
                Overflow <= '1';
            else
                Overflow <= '0';
            end if;
            -- Capture Compare
            if(Counter_Timer(Width - 1 downto 0) > (Capture(Width - 1 downto 0) - 1)) then
                PWM <= PWM_Inv;
                PWM <= not PWM_Inv;
            end if;
        end if;        
    end process;  
    Clock_Out <= Clock_Intern;
end Timer_Arch;


Jetzt habe ich mal ein bisschen mit Vivado rum gespielt und mir mal die 
Schaltung ausgeben lassen.
In dem angehängten Bild (Bild 1) ist die Eingangsstufe für den Takt 
gezeigt. Warum werden da zwei Buffer verwendet (wovon einer invertiert)?

Wenn ich mir jetzt ein Top-Design dafür erstelle und es synthetisiere 
und mir anschließend die Schaltung ausgebe, dann optimiert die Toolchain 
die Schaltung weg (siehe Bild 2):

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- Create Date:         10.02.2015 07:51:07
-- Design Name: 
-- Module Name:         Top - Top_Arch
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- Dependencies: 
-- Revision:-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Top is
    Port (  Output : out STD_LOGIC;
            Clock_In : in STD_LOGIC);
end Top;
architecture Top_Arch of Top is
    signal Compare      : std_logic;
    signal Overflow     : std_logic;
    signal PWM          : std_logic;
    signal Clock_Out    : std_logic;
    component Timer is
        Generic (   Width : integer := 8 );
        Port (      Clock_In : in STD_LOGIC;
                    Reset : in STD_LOGIC;
                    Prescaler : in STD_LOGIC_VECTOR(2 downto 0);
                    Preload : in STD_LOGIC_VECTOR(Width - 1 downto 0);
                    Capture : in STD_LOGIC_VECTOR(Width - 1 downto 0);
                    PWM_Enable : in STD_LOGIC;
                    PWM_Inv : in STD_LOGIC;
                    Compare : out STD_LOGIC;
                    Overflow : out STD_LOGIC;
                    PWM : out STD_LOGIC;
                    Clock_Out : out STD_LOGIC); 
    end component;
    -- Device Instantiation
    TT0: Timer port map(Clock_In, '0', "000", "00000000", "00000000", '0', '0', Compare, Overflow, PWM, Clock_Out);
end Top_Arch;


Warum tut er das?
Danke für die Hilfe :)

Angehängte Dateien:

Bild_1.png (4,7 KB)
Bild_2.png (4 KB)

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VHDL Timer & PWM

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